MT29F4G08ABADAWP:D Micron Technology Inc, MT29F4G08ABADAWP:D Datasheet - Page 8

• Manufacturer Part Number: MT29F4G08ABADAWP:D
• Description: MICMT29F4G08ABADAWP:D 4GB SLC NAND 34NM
• Manufacturer: Micron Technology Inc

Specifications of MT29F4G08ABADAWP:D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

General Description
Signal Descriptions
Table 1: Signal Definitions
PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. G 11/10 EN
I/O[15:0] (x16)
I/O[7:0] (x8)
Signal
LOCK
WE#
WP#
DNU
R/B#
ALE
CE#
CLE
RE#
V
V
NC
CC
SS
1
Output
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Notes:
I/O
–
–
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the asyn-
chronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
See Internal ECC and Spare Area Mapping for ECC for more information.
1. See Device and Array Organization for detailed signal connections.
2. See Asynchronous Interface Bus Operation for detailed asynchronous interface signal de-
Description
Address latch enable: Loads an address from I/O[7:0] into the address register.
Chip enable: Enables or disables one or more die (LUNs) in a target.
Command latch enable: Loads a command from I/O[7:0] into the command register.
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable the
BLOCK LOCK, connect LOCK to V
down).
Read enable: Transfers serial data from the NAND Flash to the host system.
Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash.
Write protect: Enables or disables array PROGRAM and ERASE operations.
Data inputs/outputs: The bidirectional I/Os transfer address, data, and command informa-
tion.
Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.
This signal indicates target array activity.
V
V
No connect: NCs are not internally connected. They can be driven or left unconnected.
Do not use: DNUs must be left unconnected.
CC
SS
scriptions.
: Core ground connection
: Core power supply
2
8
SS
4Gb, 8Gb: x8, x16 NAND Flash Memory
during power-up, or leave it disconnected (internal pull-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
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