MT29F4G08ABADAWP:D Micron Technology Inc, MT29F4G08ABADAWP:D Datasheet - Page 71

• Manufacturer Part Number: MT29F4G08ABADAWP:D
• Description: MICMT29F4G08ABADAWP:D 4GB SLC NAND 34NM
• Manufacturer: Micron Technology Inc

Specifications of MT29F4G08ABADAWP:D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PROGRAM PAGE (80h-10h)
Figure 44: PROGRAM PAGE (80h-10h) Operation
PROGRAM PAGE CACHE (80h-15h)
PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. G 11/10 EN
Cycle type
I/O[7:0]
RDY
Command
80h
Address
C1
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache
register, and moves the data from the cache register to the specified block and page ad-
dress in the array of the selected die (LUN). This command is accepted by the die (LUN)
when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy
with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block and
page address specified, write 80h to the command register. Unless this command has
been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the
80h to the command register clears all of the cache registers' contents on the selected
target. Then write n address cycles containing the column address and row address. Da-
ta input cycles follow. Serial data is input beginning at the column address specified. At
any time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM
FOR INTERNAL DATA INPUT (85h) commands may be issued. When data input is com-
plete, write 10h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) may be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The PROGRAM PAGE (80h-10h) command is used as the final command of a two-plane
program operation. It is preceded by one or more PROGRAM PAGE TWO-PLANE
(80h-11h) commands. Data is transferred from the cache registers for all of the ad-
dressed planes to the NAND array. The host should check the status of the operation by
using the status operations (70h, 78h).
When internal ECC is enabled, the duration of array programming time is
During
plete.
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the
selected die (LUN). After the data is copied to the data register, the cache register is avail-
Address
C2
Address
t
PROG_ECC, the internal ECC generates parity bits when error detection is com-
R1
Address
R2
Address
R3
t
t
PROG as data is transferred.
ADL
71
D
D0
IN
4Gb, 8Gb: x8, x16 NAND Flash Memory
D
D1
IN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
…
IN
D
Dn
IN
Command
10h
t
WB
Program Operations
t
PROG_ECC
t
PROG or
© 2009 Micron Technology, Inc. All rights reserved.
Command
70h
t
PROG_ECC.
Status
D
OUT