MT29F4G08ABADAWP:D Micron Technology Inc, MT29F4G08ABADAWP:D Datasheet - Page 72

• Manufacturer Part Number: MT29F4G08ABADAWP:D
• Description: MICMT29F4G08ABADAWP:D 4GB SLC NAND 34NM
• Manufacturer: Micron Technology Inc

Specifications of MT29F4G08ABADAWP:D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PDF: 09005aef83b25735
m60a_4gb_nand.pdf – Rev. G 11/10 EN
able for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die
(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when
busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page
address specified, write 80h to the command register. Unless this command has been
preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to
the command register clears all of the cache registers' contents on the selected target.
Then write n address cycles containing the column address and row address. Data in-
put cycles follow. Serial data is input beginning at the column address specified. At any
time during the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR
INTERNAL DATA INPUT (85h) commands may be issued. When data input is complete,
write 15h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for
previous program cache operation, to copy data from the cache register to the data reg-
ister, and then to begin moving the data register contents to the specified page and
block address.
To determine the progress of
alternatively, the status operations (70h, 78h) can be used. When the LUN’s status
shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host
should check the status of the FAILC bit to see if a previous cache operation was successful.
If, after
out issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY
until it is 1. The host should then check the status of the FAIL and FAILC bits.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
used to select only one die (LUN) for status output. Use of the READ STATUS (70h) com-
mand could cause more than one die (LUN) to respond, resulting in bus contention.
The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a two-
plane program cache operation. It is preceded by one or more PROGRAM PAGE TWO-
PLANE (80h-11h) commands. Data for all of the addressed planes is transferred from
the cache registers to the corresponding data registers, then moved to the NAND Flash
array. The host should check the status of the operation by using the status operations
(70h, 78h).
t
CBSY, the host wants to wait for the program cache operation to complete, with-
t
CBSY to allow the data register to become available from a
72
t
CBSY, the host can monitor the target's R/B# signal or,
4Gb, 8Gb: x8, x16 NAND Flash Memory
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Program Operations
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