Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 19

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following features are common to both the ESCC and
the CMOS SCC:
DS971820600
Zilog
Two independent full-duplex channels
Synchronous/Isochronous data rates:
Asynchronous capabilities
- 5, 6, 7 or 8 bits/character (capable of handling
- 1, 1.5, or 2 stop bits
- Odd or even parity
- Times 1, 16, 32 or 64 clock modes
- Break generation and detection
- Parity, overrun and framing error detection
Byte oriented synchronous capabilities:
SDLC/HDLC capabilities:
- Up to 1/4 of the PCLK using external clock source
- Up to 5 Mbits/sec at 20 MHz PCLK (ESCC).
- Internal or external character synchronization
- One or two sync characters (6 or 8 bits/sync
- Automatic Cyclic Redundancy Check (CRC)
- Abort sequence generation and checking
- Automatic zero insertion and detection
- Automatic flag insertion between messages
- Address field recognition
- I-field residue handling
- CRC generation/detection
- SDLC loop mode with EOP recognition/loop entry
4 bits/character or less)
character) in separate registers
generation/detection
and exit
PS009801-0301
P R E L I M I N A R Y
The following features are implemented in the ESCC
the Z80182/Z8L182 only:
Note: The ESCC
programmed to divide-by-two mode when operating above
the following conditions:
NRZ, NRZI or FM encoding/decoding. Manchester
Code Decoding (Encoding with External Logic).
Baud Rate Generator in each Channel
Digital Phase-Locked Loop (DPLL) for Clock Recovery
Crystal Oscillator
New 32-bit CRC-32 (Ethernet Polynomial)
ESCC Programmable Clock
- programmed to be equal to system clock
- programmed by Z80182 Enhancement Register
divided by one or two
– PHI > 20 MHz at 5.0V
– PHI > 10 MHz at 3.0V
™
programmable clock must be
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
3-19
™
for