Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 26

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Zilog
The Z80182 Rev DA implements double buffering for the
transmitter in 16450 mode and sets the TEMT bit in the LSR
Register automatically.
When this feature is enabled and character delay emulation
is being used (see Figure 9):
1. The PC THRE bit in the LSR Register is set when the
2. PC Host writes to the 16450 THR Register;
3. Whenever the Z80182 TSR buffer is empty and one
4. Restart character delay timer (timer reloads and counts
5. Whenever the TSR buffer is full, the TEMT bit in MPU
3-26
Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER
THR Register is empty;
character delay timer is in a timed-out state, the byte
from the THR Register is transferred to the TSR buffer;
the timer is in timed-out state after FIFO Reset or after
Host TEMT is set. This allows a dual write to THR when
Host TEMT is set.
down) with byte transfer from THR Register to the TSR
buffer;
LSR Register is reset with no delay;
Host TEMT = 1 if - THRE = 1
Note: MPU sees TSR bit in the LSR Register as TEMT bit
(MPU TEMT) TSRE = 1
Host & MPU THRE = 1
- TSRE = 1
- Emulation delay timer is timed out
Figure 9. TEMT Emulation Logic Implementation
Empty/Full
Empty/Full
0
0
PS009801-0301
P R E L I M I N A R Y
THR to TSR
Host Write
Shift Reg.
Emulation
Register
Transmit
16450
transfer
THR
TSR
delay
6. MPU reads TSR buffer;
7. TEMT bit in LSR Register for MPU is set with no delay
8. When the TSR buffer is read by MPU and THR Register
The PC THRE bit in the LSR Register is reset whenever the
THR Register is full and set whenever THR Register is
empty.
MPU IREQ and DMA Request for the transmit data is
trigger whenever TSR buffer is full and cleared whenever
TSR buffer is empty.
If character delay emulation is not used the TEMT bit in the
LSR Register is set whenever both the THR Register and
the TSR buffer are both empty. The Host TEMT bit is clear
if there is data in either the TSR buffer of THR Register.
whenever the TSR buffer is empty;
is empty and one character delay timer reaches zero,
the TEMT bit in the LSR Register for Host is set from 0
to 1.
Byte Transfer if:
- THRE=0;
- TSR = 1;
- Character delay timer is timed out.
Note: Timer reloads and counts down
whenever data is transferred from THR to TSR.
Added TSR Buffer for the
transmit data
Z
ILOG
I
NTELLIGENT
DS971820600
Z80182/Z8L182
P
ERIPHERAL