Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 97

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
These AC parameters values are preliminary and subject to change without notice.
[1] Open-drain output, measured with open-drain test load.
[2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[4] Units equal to TcPc
DS971820600
Zilog
No.
1
2
3
4
No.
1
2
3
4
5
6
7
8
9
No.
1
2
3
4
5
6
7
8
9
10
Symbol
TsPIA(RD)
ThPIA(RD)
TdWR
T
Symbol
TsA(IORQf)
TsIOf(WRf)
TsIOf(RDf)
ThIOR(WR
ThIOR(RD
TdRDf(DO)
T
T
THD(WR
F
H
S
WR
D(WR
RD
Symbol
TdRxC(REQ)
TdRxC(W)
TdRxC(SY)
TdRxC(INT)
TdTxC(REQ)
TdTxC(W)
TdTxC(DRQ)
TdTxC(INT)
TdSY(INT)
TdExT(INT)
R
F
F
(PIA)
(DO)
(PIA)
R
)
R
)
R
R
)
)
Parameter
Port Data Input Setup to /RD Fall
Port Data Input Hold From /RD Rise
Port Data Output Delay From /WR Fall
Port Data Output Float From /WR Fall
Parameter
Address to /IORQ Fall Setup
/IORQ Fall to /WR Fall Setup
/IORQ Fall to /RD Fall Setup
/IORQ Rise From /WR Rise Hold
/IORQ Rise From /RD Rise Hold
/RD Fall to Data Out Valid Delay
/RD Rise to Data Out Valid Hold
Data In to /WR Fall Setup
Data In From /WR Rise Hold
Table D. Z85230 System Timing Table
Parameter
/RxC to /W//REQ Valid
/RxC to /Wait Inactive
/RxC to /SYNC Valid
/RxC to /INT Valid
/TxC to /W//REQ Valid
/TxC to /Wait Inactive
/TxC to /DTR//REQ Valid
/TxC to /INT Valid
/SYNC to /INT Valid
/DCD or /CTS to /INT Valid
Table F. External Bus Master Timing
PS009801-0301
P R E L I M I N A R Y
Table E. I/O Port Timing
Min
Min
20
10
50
10
0
0
0
0
0
0
Min
13
13
15
9
8
8
7
9
2
3
Z8L182
20 MHz
Z8L182
20 MHz
20 MHz
Max
Max
60
50
0
8
Max
18
18
13
22
12
15
11
14
6
9
Z
ILOG
Min
Min
50
10
20
5
0
0
0
0
0
0
I
33 MHz
33 MHz
NTELLIGENT
Z80182
Z80182
Notes [4]
[1,2]
[1,2]
[1,3]
[1,3]
[2]
[2]
[3]
[3]
[1]
[1]
Z80182/Z8L182
Max
Max
45
60
0
P
ERIPHERAL
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