PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 177

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

11.0
Depending on the device selected and features
enabled, there are up to seven ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register, writes
to the Output Latch (LAT) register.
Setting a TRIS bit (= 1 ) makes the corresponding port
pin an input (putting the corresponding output driver in
a High-Impedance mode). Clearing a TRIS bit (= 0 )
makes the corresponding port pin an output (i.e., put
the contents of the corresponding LAT bit on the
selected pin).
The Output Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in
FIGURE 11-1:
 2011 Microchip Technology Inc.
device)
Note 1:
RD LAT
Data
Bus
WR LAT
or PORT
WR TRIS
RD TRIS
RD PORT
I/O PORTS
I/O pins have diode protection to V
TRIS Latch
Data Latch
CKx
CKx
D
D
GENERIC I/O PORT
OPERATION
Q
Q
Q
EN
EN
D
DD
and V
Figure
I/O Pin
Input
Buffer
SS
.
11-1.
(1)
Preliminary
PIC18F66K80 FAMILY
11.1
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
All of the digital ports are 5.5V input tolerant. The
analog ports have the same tolerance, having clamping
diodes implemented internally.
11.1.1
When used as digital I/O, the output pin drive strengths
vary, according to the pins’ grouping to meet the needs
for a variety of applications. In general, there are two
classes of output pins, in terms of drive capability:
• Outputs designed to drive higher current loads
• Outputs with lower drive levels, but capable of
For more details, see “Absolute Maximum Ratings” in
Section 31.0 “Electrical Characteristics”
11.1.2
Five of the I/O ports (PORTB, PORTD, PORTE,
PORTF and PORTG) implement configurable weak
pull-ups on all pins. These are internal pull-ups that
allow floating digital input signals to be pulled to a
consistent level without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU, RFPU and RGPU (PADCFG1<7:4>) for the
other ports.
Additionally, the PORTB pull-up resistors can be
enabled individually using the WPUB register. Each bit
in the register corresponds to a bit on PORTB.
such as LEDs:
- PORTA
- PORTC
driving normal digital circuit loads with a high input
impedance. Able to drive LEDs, but only those
with smaller current requirements:
- PORTD
- PORTF
Note 1: These ports are not available on 28-pin
I/O Port Pin Capabilities
2: These ports are not available on 28-pin
PIN OUTPUT DRIVE
PULL-UP CONFIGURATION
(2)
(1)
devices.
or 40/44-pin devices
– PORTB
– PORTE
– PORTG
(1)
(2)
DS39977C-page 177
DD
input levels.
.