PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 81

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

5.0
The PIC18F66K80 family devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
i)
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”
WDT Resets are covered in
Timer (WDT)”
FIGURE 5-1:
 2011 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: This is the INTOSC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
Power-on Reset (POR)
MCLR Reset during Normal Operation
MCLR Reset during Power-Managed modes
Watchdog Timer (WDT) Reset (during
execution)
Configuration Mismatch (CM) Reset
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: See
Instruction
INTOSC
RESET
OST/PWRT
Pointer
32 s
Stack
.
( )_IDLE
Brown-out
V
Time-out
(1)
Detect
Sleep
DD
Table 5-2
WDT
Reset
Rise
OST
PWRT
Stack Full/Underflow Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLRE
10-Bit Ripple Counter
11-Bit Ripple Counter
POR Pulse
for time-out situations.
BOREN
Section 28.2 “Watchdog
1024 Cycles
65.5 ms
Preliminary
.
PIC18F66K80 FAMILY
A simplified block diagram of the On-Chip Reset Circuit
is shown in
5.1
Device Reset events are tracked through the RCON
register
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in
of Registers”
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 10.0 “Interrupts”
Section 5.4 “Brown-out Reset (BOR)”
(Register
RCON Register
Figure
.
5-1). The lower five bits of the regis-
5-1.
S
R
Section 5.7 “Reset State
. BOR is covered in
DS39977C-page 81
Q
Enable OST
Enable PWRT
Chip_Reset
.
(2)