PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 364

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
23.2
23.2.1
REGISTER 23-1:
DS39977C-page 364
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-2
bit 1
bit 0
Note 1:
U-0
—
2:
3:
A/D Registers
These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return random values.
Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of the ADC input, for
finer resolution CTMU time measurements.
A/D CONTROL REGISTERS
Unimplemented: Read as ‘ 0 ’
CHS<4:0>: Analog Channel Select bits
00000 = Channel 00 (AN0)
00001 = Channel 01 (AN1)
00010 = Channel 02 (AN2)
00011 = Channel 03 (AN3)
00100 = Channel 04 (AN4)
00101 = Channel 05 (AN5)
00110 = Channel 06 (AN6)
00111 = Channel 07 (AN7)
01000 = Channel 08 (AN8)
01001 = Channel 09 (AN9)
01010 = Channel 10 (AN10)
01011 = (Reserved)
01100 = (Reserved)
01101 = (Reserved)
01110 = (Reserved)
01111 = (Reserved)
GO/DONE: A/D Conversion Status bit
1 = A/D cycle is in progress. Setting this bit starts an A/D conversion cycle. The bit is cleared
0 = A/D conversion has completed or is not in progress
ADON: A/D On bit
1 = A/D Converter is operating
0 = A/D conversion module is shut off and consuming no operating current
R/W-0
CHS4
automatically by hardware when the A/D conversion is completed.
ADCON0: A/D CONTROL REGISTER 0
W = Writable bit
‘1’ = Bit is set
R/W-0
CHS3
(2)
(2))
(2))
(2))
(2)
(1,2)
(1,2)
(1,2)
R/W-0
CHS2
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
10000 = (Reserved)
10001 = (Reserved)
10010 = (Reserved)
10011 = (Reserved)
10100 = (Reserved)
10101 = (Reserved)
10110 = (Reserved)
10111 = (Reserved)
11000 = (Reserved)
11001 = (Reserved)
11010 = (Reserved)
11011 = (Reserved)
11100 = (MUX disconnect)
11101 = Channel 29 (temperature diode)
11110 = Channel 30 (V
11111 = Channel 31 (1.024V band gap)
R/W-0
CHS1
R/W-0
CHS0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
DDCORE
 2011 Microchip Technology Inc.
(3)
x = Bit is unknown
GO/DONE
)
R/W-0
R/W-0
ADON
bit 0