PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 479

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

28.3.3
The difference in the two regulators’ operation arises
with Sleep mode. The ultra low-power regulator gives
the device the lowest current in the Regulator Enabled
mode.
The on-chip regulator can go into a lower power mode
when the device goes to Sleep by setting the REGSLP
bit (WDTCON<7>). This puts the regulator in a standby
mode so that the device consumes much less current.
The on-chip regulator can also go into the Ultra Low-
Power mode, which consumes the lowest current
possible with the regulator enabled. This mode is
controlled by the RETEN bit (CONFIG1L<0>) and
SRETEN bit (WDTCON<4>).
TABLE 28-3:
 2011 Microchip Technology Inc.
PIC18 F XXK80
PIC18 F XXK80
PIC18 F XXK80
PIC18 F XXK80
PIC18 F XXK80
PIC18 LF XXK80
PIC18 LF XXK80
Note 1:
Device
2:
x — Indicates that V
The Ultra Low-Power regulator should be disabled (RETEN = 1 , ULP disabled) on PIC18 LF XXK80
devices to obtain the lowest possible Sleep current.
OPERATION OF REGULATOR IN
SLEEP
SLEEP MODE REGULATOR SETTINGS
Regulator Bypass mode (Sleep)
Ultra Low-Power mode (Sleep)
Normal Operation (Sleep)
Normal Operation (Sleep)
Low-Power mode (Sleep)
Low-Power mode (Sleep)
IT
Power Mode
status is invalid.
Reserved
(2)
Preliminary
(2)
PIC18F66K80 FAMILY
WDTCON<7>
The various modes of regulator operation are shown in
Table
When the ultra low-power regulator is in Sleep mode,
the internal reference voltages in the chip will be shut
off and any interrupts referring to the internal reference
will not wake up the device. If the BOR or LVD is
enabled, the regulator will keep the internal references
on and the lowest possible current will not be achieved.
When using the ultra low-power regulator in Sleep
mode, the device will take about 250  s to start
executing code after it wakes up.
(1)
REGSLP
0
1
0
1
x
x
x
28-3.
WDTCON<4>
Don’t Care
SRETEN
x
x
0
0
1
x
DS39977C-page 479
CONFIG1L<0>
RETEN
1
1
0
0
0
0
1