PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 451

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

27.9.1
The microcontroller clock frequency generated from a
PLL circuit is subject to a jitter, also defined as Phase
Jitter or Phase Skew. For its PIC18 Enhanced micro-
controllers, Microchip specifies phase jitter ( P
being 2% (Gaussian distribution, within 3 standard
deviations, see Parameter F13 in
Jitter ( T
FIGURE 27-5:
Once these considerations are taken into account, it is
possible to show that the relation between the jitter and
the total frequency error can be defined as:
where jitter is expressed in terms of time and NBT is the
Nominal Bit Time.
 2011 Microchip Technology Inc.
jitter
Nominal Clock
Clock with Jitter
CAN Bit Time
with Jitter
) as being 2 * P
EXTERNAL CLOCK, INTERNAL
CLOCK AND MEASURABLE JITTER
IN HS-PLL BASED OSCILLATORS
f
=
----------------------- -
10 NBT
T

jitter
EFFECTS OF PHASE JITTER ON THE MICROCONTROLLER CLOCK
AND CAN BIT TIME
jitter
=
.
----------------------- -
10 NBT
2 P


Table
jitter
31-7) and Total
jitter
) as
Preliminary
Phase Skew (Jitter)
CAN Bit Jitter
PIC18F66K80 FAMILY
The CAN protocol uses a bit-stuffing technique that
inserts a bit of a given polarity following five bits with the
opposite polarity. This gives a total of 10 bits transmit-
ted without resynchronization (compensation for jitter
or phase error).
Given the random nature of the added jitter error, it can
be shown that the total error caused by the jitter tends
to cancel itself over time. For a period of 10 bits, it is
necessary to add only two jitter intervals to correct for
jitter induced error: one interval in the beginning of the
10-bit period and another at the end. The overall effect
is shown in
For example, assume a CAN bit rate of 125 Kb/s, which
gives an NBT of 8 µs. For a 16 MHz clock generated
from a 4x PLL, the jitter at this clock frequency is:
and resultant frequency error is:
2
-------------------------------------- -
10

2%


1.25

Figure

8
10
-------------------
16 MHz
10
6 –
1
9 –
27-5.


=
=
3.125
-----------------
16
0.02
10
10
6
–
5
=
=
DS39977C-page 451
1.25ns
0.0031%