PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 400

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
EXAMPLE 27-1:
EXAMPLE 27-2:
DS39977C-page 400
WakeupInterrupt
NoInterrupt
ConfigWait:
; Save application required context.
; Poll interrupt flags and determine source of interrupt
; This was found to be CAN interrupt
; TempCANCON and TempCANSTAT are variables defined in Access Bank low
MOVFF
MOVFF
MOVF
ANDLW
ADDWF
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BCF
;
; User code to handle wake-up procedure
;
;
; Continue checking for other interrupt source or return from here
…
…
; Request Configuration mode.
MOVLW
MOVWF
; A request to switch to Configuration mode may not be immediately honored.
; Module will wait for CAN bus to be idle before switching to Configuration Mode.
; Request for other modes such as Loopback, Disable etc. may be honored immediately.
; It is always good practice to wait and verify before continuing.
MOVF
ANDLW
TSTFSZ WREG
BRA
; Module is in Configuration mode now.
; Modify configuration registers as required.
; Switch back to Normal mode to be able to communicate.
CANCON, TempCANCON
CANSTAT, TempCANSTAT
TempCANSTAT, W
B’00001110’
PCL, F
NoInterrupt
ErrorInterrupt
TXB2Interrupt
TXB1Interrupt
TXB0Interrupt
RXB1Interrupt
RXB0Interrupt
PIR3, WAKIF
B’10000000’
CANCON
CANSTAT, W
B’10000000’
ConfigWait
CHANGING TO CONFIGURATION MODE
WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS
TX/RX BUFFERS
Preliminary
; Save CANCON.WIN bits
; This is required to prevent CANCON
; from corrupting CAN buffer access
; in-progress while this interrupt
; occurred
; Save CANSTAT register
; This is required to make sure that
; we use same CANSTAT value rather
; than one changed by another CAN
; interrupt.
; Retrieve ICODE bits
; Perform computed GOTO
; to corresponding interrupt cause
; 000 = No interrupt
; 001 = Error interrupt
; 010 = TXB2 interrupt
; 011 = TXB1 interrupt
; 100 = TXB0 interrupt
; 101 = RXB1 interrupt
; 110 = RXB0 interrupt
; 111 = Wake-up on interrupt
; Clear the interrupt flag
; PC should never vector here. User may
; place a trap such as infinite loop or pin/port
; indication to catch this error.
; Set to Configuration Mode.
; Read current mode state.
; Interested in OPMODE bits only.
; Is it Configuration mode yet?
; No. Continue to wait...
 2011 Microchip Technology Inc.