PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 225

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

14.8.4
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single Pulse mode is enabled by setting the
T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE
bit (T1GCON<3>). The Timer1 will be fully enabled on
the next incrementing edge.
On the next trailing edge of the pulse, the T1GGO/
T1DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until
the T1GGO/T1DONE bit is once again set in software.
FIGURE 14-6:
 2011 Microchip Technology Inc.
TMR1GE
T1GSPM
T1DONE
T1GPOL
T1GVAL
T1GGO/
T1G_IN
Timer1
T1CKI
TIMER1 GATE SINGLE PULSE
MODE
TIMER1 GATE SINGLE PULSE MODE
N
Counting Enabled on
Rising Edge of T1G
Set by Software
Preliminary
N + 1
PIC18F66K80 FAMILY
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/T1DONE bit. (For timing details,
see
Simultaneously enabling the Toggle and Single Pulse
modes will permit both sections to work together. This
allows the cycle times on the Timer1 gate source to be
measured. (For timing details, see
14.8.5
When the Timer1 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the T1GVAL bit
(T1GCON<2>). This bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Figure
Cleared by Hardware on
Falling Edge of T1GVAL
14-6.)
TIMER1 GATE VALUE STATUS
N + 2
Figure
DS39977C-page 225
14-7.)