PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 179

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

11.1.3
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bits in the ODCON
register.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure
it is pulled up to the higher voltage level.
REGISTER 11-3:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPOD
R/W-0
11-2). When a digital logic high signal is output,
OPEN-DRAIN OUTPUTS
SSPOD: SPI Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP5OD: CCP5 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP4OD: CCP4 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP3OD: CCP3 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP2OD: CCP2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP1OD: CCP1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U2OD: UART2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U1OD: UART1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP5OD
R/W-0
ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
CCP4OD
R/W-0
CCP3OD
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
CCP2OD
R/W-0
FIGURE 11-2:
3.3V
V
CCP1OD
DD
PIC18F66K80
R/W-0
(at logic ‘1’)
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
TX
x = Bit is unknown
X
R/W-0
U2OD
3.3V
DS39977C-page 179
+5V
R/W-0
U1OD
5V
bit 0