PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 280

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
20.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the P1A pin, while the complementary PWM output
signal is output on the P1B pin (see
mode can be used for half-bridge applications, as
shown in
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in
half-bridge power devices. The value of the P1DC<6:0>
bits of the ECCP1DEL register sets the number of
instruction cycles before the output is driven active. If the
value is greater than the duty cycle, the corresponding
output remains inactive during the entire cycle. For more
details on the dead-band delay operations, see
Section 20.4.6 “Programmable Dead-Band Delay
Mode”
FIGURE 20-7:
DS39977C-page 280
.
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
Figure
HALF-BRIDGE MODE
20-7, or for full-bridge applications,
EXAMPLE OF HALF-BRIDGE APPLICATIONS
P1A
P1B
Figure
P1A
P1B
20-6). This
FET
Driver
FET
Driver
Preliminary
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the port data latches, the associated TRIS bits must be
cleared to configure P1A and P1B as outputs.
FIGURE 20-6:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
Load
(2)
(2)
V+
2: Output signals are shown as active-high.
(1)
td
PR2 register.
Pulse Width
Load
Period
td
EXAMPLE OF
HALF-BRIDGE PWM
OUTPUT
 2011 Microchip Technology Inc.
FET
Driver
FET
Driver
+
-
+
-
(1)
Period
(1)