PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 310

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
21.4.3.5
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPIF, must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1 ), SCL will be held
low (clock stretch) following each data transfer. The
clock
(SSPCON1<4>).
Stretching”
DS39977C-page 310
must
for more details.
Reception
be
released
See
Section 21.4.4
by
setting
bit,
“Clock
CKP
Preliminary
21.4.3.6
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin SCL is held low regard-
less of SEN (see
for more details). By stretching the clock, the master
will be unable to assert another clock pulse until the
slave is done preparing the transmit data. The transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, the SCL pin
should be enabled by setting bit, CKP (SSPCON1<4>).
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
enabled by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
Transmission
Section 21.4.4 “Clock Stretching”
 2011 Microchip Technology Inc.
(Figure
21-10).