PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 309

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

21.4.3.4
Unlike 5-bit masking, 7-Bit Address Masking mode
uses a mask of up to 8 bits (in 10-bit addressing) to
define a range of addresses that can be Acknowl-
edged, using the lowest bits of the incoming address.
This allows the module to Acknowledge up to
127 different addresses with 7-bit addressing, or
255 with 10-bit addressing (see
mode is the default configuration of the module, which
is selected when MSSPMSK is unprogrammed (‘ 1 ’).
The address mask for 7-Bit Address Masking mode is
stored in the SSPMSK register, instead of the
SSPCON2 register. SSPMSK is a separate hardware
register within the module, but it is not directly address-
able. Instead, it shares an address in the SFR space
with the SSPADD register. To access the SSPMSK reg-
ister, it is necessary to select MSSP mode, ‘ 1001 ’
(SSPCON1<3:0> = 1001 ) and then read or write to the
location of SSPADD.
To use 7-Bit Address Masking mode, it is necessary to
initialize SSPMSK with a value before selecting the I
Slave Addressing mode. Thus, the required sequence
of events is:
1.
2.
3.
EXAMPLE 21-3:
 2011 Microchip Technology Inc.
7-Bit Addressing:
10-Bit Addressing:
Select
(SSPCON2<3:0> = 1001 ).
Write the mask value to the appropriate
SSPADD register address (FC8h).
Set
(SSPCON2<3:0> = 0111 for 10-bit addressing,
0110 for 7-bit addressing).
SSPADD<7:1>
SSPMSK<7:1>
Addresses Acknowledged = ACh, A8h, A4h, A0h
SSPADD<7:0>
SSPMSK<5:1>
Addresses Acknowledged = ACh, A8h, A4h, A0h
the
7-Bit Address Masking Mode
appropriate
SSPMSK
ADDRESS MASKING EXAMPLES IN 7-BIT MASKING MODE
= 1010 000
= 1111 001
= 1010 0000 (The two MSb are ignored in this example since they are not affected)
= 1111 0011
I
2
Access
C
Example
Slave
21-3). This
mode
mode
Preliminary
2
C
PIC18F66K80 FAMILY
Setting or clearing mask bits in SSPMSK behaves in
the opposite manner of the ADMSK bits in 5-Bit
Address Masking mode. That is, clearing a bit in
SSPMSK causes the corresponding address bit to be
masked; setting the bit requires a match in that
position. SSPMSK resets to all ‘ 1 ’s upon any Reset
condition and, therefore, has no effect on the standard
MSSP operation until written with a mask value.
With 7-bit addressing, SSPMSK<7:1> bits mask the
corresponding address bits in the SSPADD register.
For
(SSPMSK<n> = 0 ),
address bit is ignored (SSPADD<n> = x ). For the mod-
ule to issue an address Acknowledge, it is sufficient to
match only on addresses that do not have an active
address mask.
With 10-bit addressing, SSPMSK<7:0> bits mask the
corresponding address bits in the SSPADD register.
For any SSPMSK bits that are active (= 0 ), the
corresponding SSPADD address bit is ignored
(SSPADD<n> = x ).
Note:
any
The two Most Significant bits of the
address are not affected by address
masking.
SSPMSK
the
bits
corresponding
that
DS39977C-page 309
are
SSPADD
active