PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 399

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 27-2:
 2011 Microchip Technology Inc.
Mode 0
Mode 1,2
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3-1,4-0
bit 0
bit 4-0
Note 1:
2:
To achieve maximum power saving and/or able to wake-up on CAN bus activity, switch the CAN module in
Disable/Sleep mode before putting the device to Sleep.
If the buffer is configured as a receiver, the EICODE bits will contain ‘ 10000 ’ upon interrupt.
OPMODE2
OPMODE2
bit 7
OPMODE<2:0>: Operation Mode Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable/Sleep mode
000 = Normal mode
Mode 0:
Unimplemented: Read as ‘ 0 ’
Mode 0:
ICODE<2:0>: Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code
indicates the source of the interrupt. By copying ICODE<3:1> to WIN<3:0> (Mode 0) or EICODE<4:0>
to EWIN<4:0> (Mode 1 and 2), it is possible to select the correct buffer to map into the Access Bank area.
See
No interrupt
CAN bus error interrupt
TXB2 interrupt
TXB1 interrupt
TXB0 interrupt
RXB1 interrupt
RXB0 interrupt
Wake-up interrupt
RXB0 interrupt
RXB1 interrupt
RX/TX B0 interrupt
RX/TX B1 interrupt
RX/TX B2 interrupt
RX/TX B3 interrupt
RX/TX B4 interrupt
RX/TX B5 interrupt
Mode 0:
Unimplemented: Read as ‘ 0 ’
Mode 1, 2:
EICODE<4:0>: Interrupt Code bits
See ICODE<3:1> above.
Example 27-2
R-1
R-1
CANSTAT: CAN STATUS REGISTER
(1)
(1)
OPMODE1
OPMODE1
for a code example. To simplify the description, the following table lists all five bits.
R-0
R-0
(1)
(1)
W = Writable bit
‘1’ = Bit is set
OPMODE0
OPMODE0
Mode 0
00000
00010
00100
00110
01000
01010
01100
00010
-----
-----
-----
-----
-----
-----
-----
-----
R-0
R-0
Preliminary
(1)
(1)
(1)
EICODE4 EICODE3 EICODE2 EICODE1
PIC18F66K80 FAMILY
R-0
R-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Mode 1
ICODE2
00000
00010
00100
00110
01000
10001
10000
01110
10000
10001
10010
10011
10100
10101
10110
10111
R-0
R-0
ICODE1
R-0
R-0
00000
00010
00100
00110
01000
-----
10000
01110
10000
10000
10010
10011
10100
10101
10110
10111
Mode 2
x = Bit is unknown
ICODE0
R-0
R-0
DS39977C-page 399
(2)
(2)
(2)
(2)
(2)
(2)
EICODE0
U-0
R-0
—
bit 0