PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 89

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

5.7
Most registers are unaffected by a Reset. Their status
is unknown on a Power-on Reset and unchanged by all
other Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
CM, POR and BOR, are set or cleared differently in dif-
TABLE 5-3:
 2011 Microchip Technology Inc.
Power-on Reset
RESET Instruction
Brown-out Reset
MCLR Reset during
Power-Managed Run modes
MCLR Reset during
Power-Managed Idle modes and
Sleep mode
WDT Time-out during Full Power
or Power-Managed Run modes
MCLR Reset during Full-Power
execution
Stack Full Reset (STVREN = 1 )
Stack Underflow Reset
(STVREN = 1 )
Stack Underflow Error (not an
actual Reset, STVREN = 0 )
WDT Time-out during
Power-Managed Idle or Sleep
modes
Interrupt Exit from
Power-Managed modes
Legend: u = unchanged
Note 1:
2:
Reset State of Registers
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
Reset state is ‘ 1 ’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01 and SBOREN = 1 ); otherwise, the Reset state is ‘ 0 ’.
Condition
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Counter
Program
PC + 2
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(1)
SBOREN CM
u
u
u
u
u
u
u
u
u
u
u
Preliminary
1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
PIC18F66K80 FAMILY
1
u
1
u
u
u
u
u
u
u
u
u
ferent Reset situations, as indicated in
These bits are used in software to determine the nature
of the Reset.
Table 5-4
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
RCON Register
RI
1
0
1
u
u
u
u
u
u
u
u
u
TO
1
u
1
1
1
0
u
u
u
u
0
u
describes the Reset states for all of the
PD
1
u
1
u
0
u
u
u
u
u
0
0
POR BOR STKFUL STKUNF
0
u
u
u
u
u
u
u
u
u
u
u
0
u
0
u
u
u
u
u
u
u
u
u
STKPTR Register
DS39977C-page 89
0
u
u
u
u
u
u
1
u
u
u
u
Table
0
u
u
u
u
u
u
u
1
1
u
u
5-3.