PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 250

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
18.4.2
There is a small amount of capacitance from the inter-
nal A/D Converter sample capacitor as well as stray
capacitance from the circuit board traces and pads that
affect the precision of capacitance measurements. A
measurement of the stray capacitance can be taken by
making sure the desired capacitance to be measured
has been removed.
After removing the capacitance to be measured:
1.
2.
3.
4.
5.
6.
Where:
• I is known from the current source measurement
• t is a fixed delay
• V is measured by performing an A/D conversion
DS39977C-page 250
step
Initialize the A/D Converter and the CTMU.
Set EDG1STAT (= 1 ).
Wait for a fixed delay of time, t .
Clear EDG1STAT.
Perform an A/D conversion.
Calculate the stray and A/D sample capacitances:
C
CAPACITANCE CALIBRATION
OFFSET
= C
STRAY
+ C
AD
= (I • t)/V
Preliminary
This measured value is then stored and used for
calculations of time measurement or subtracted for
capacitance measurement. For calibration, it is
expected that the capacitance of C
approximately known; C
An iterative process may be required to adjust the time,
t , that the circuit is charged to obtain a reasonable volt-
age reading from the A/D Converter. The value of t may
be determined by setting C
and solving for t . For example, if C
calculated to be 11 pF, and V is expected to be 70% of
V
or 63  s.
See
capacitance calibration.
DD
or 2.31V, t would be:
Example 18-3
(4 pF + 11 pF) • 2.31V/0.55 A
for a typical routine for CTMU
 2011 Microchip Technology Inc.
AD
OFFSET
is approximately 4 pF.
to a theoretical value
STRAY
STRAY
is theoretically
+ C
AD
is