PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 484

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
TABLE 28-4:
28.6.1
The program memory may be read to, or written from,
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPx bits have no direct
effect. CPx bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTx Configuration bit is ‘ 0 ’.
The EBTRx bits control table reads. For a block of user
memory with the EBTRx bit set to ‘ 0 ’, a table read
instruction that executes from within that block is allowed
to read. A table read instruction that executes from a
FIGURE 28-7:
DS39977C-page 484
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L
30000Dh CONFIG7H
Legend: Shaded cells are unimplemented.
File Name
TBLPTR = 0008FFh
Results: All table writes are disabled to Blockn whenever WRTx = 0
Register Values
PROGRAM MEMORY
CODE PROTECTION
PC = 00BFFEh
PC = 003FFEh
SUMMARY OF CODE PROTECTION REGISTERS
TABLE WRITE (WRTx) DISALLOWED
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
Program Memory
WRTC
Bit 5
Preliminary
—
—
—
—
—
TBLWT*
TBLWT*
Bit 4
—
—
—
—
—
—
illustrate table write and table read protection.
location outside of that block is not allowed to read and
will result in reading ‘ 0 ’s. Figures
Note:
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
EBTR3
WRT3
Bit 3
CP3
—
—
—
.
Code protection bits may only be written
to a ‘ 0 ’ from a ‘ 1 ’ state. It is not possible to
write a ‘ 1 ’ to a bit in the ‘ 0 ’ state. Code
protection bits are only set to ‘ 1 ’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
programming
information.
Configuration Bit Settings
EBTR2
WRT2
Bit 2
CP2
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
—
—
—
 2011 Microchip Technology Inc.
Refer
specification
EBTR1
WRT1
Bit 1
CP1
—
—
—
28-7
to
the
through
for
EBTR0
WRT0
Bit 0
CP0
device
—
—
—
more
28-9