PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 227

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

15.0
The Timer2 module incorporates the following features:
• Eight-bit Timer and Period registers (TMR2 and
• Both registers are readable and writable
• Software programmable prescaler
• Software programmable postscaler
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
The module is controlled through the T2CON register
(Register
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure
15.1
In normal operation, TMR2 is incremented from 00h on
each clock (F
clock input gives the prescale options of direct input,
divide-by-4 or divide-by-16. These are selected by the
prescaler control bits, T2CKPS<1:0> (T2CON<1:0>).
REGISTER 15-1:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1-0
PR2, respectively)
(1:1, 1:4 and 1:16)
(1:1 through 1:16)
MSSP module
U-0
—
15-1.
TIMER2 MODULE
Timer2 Operation
15-1) that enables or disables the timer, and
OSC
Unimplemented: Read as ‘ 0 ’
T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
T2OUTPS3
/4). A four-bit counter/prescaler on the
R/W-0
T2CON: TIMER2 CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
T2OUTPS2
R/W-0
T2OUTPS1
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
T2OUTPS0
R/W-0
The value of TMR2 is compared to that of the Period reg-
ister, PR2, on each clock cycle. When the two values
match, the comparator generates a match signal as the
timer output. This signal also resets the value of TMR2
to 00h on the next cycle and drives the output counter/
postscaler. (See
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset – Power-on Reset (POR),
TMR2 is not cleared when T2CON is written.
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
Note:
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see
Register
TMR2ON
R/W-0
Section 15.2 “Timer2 Interrupt”
19-2.
x = Bit is unknown
T2CKPS1
R/W-0
Register 20-2
DS39977C-page 227
T2CKPS0
R/W-0
.)
bit 0
and