PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 184

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

corresponding Data Direction and Output Latch registers
PIC18F66K80 FAMILY
11.3
PORTB is an eight-bit wide, bidirectional port. The
are TRISB and LATB. All pins on PORTB are digital only.
EXAMPLE 11-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
DS39977C-page 184
CLRF
CLRF
MOVLW
MOVWF
PORTB, TRISB and
LATB Registers
PORTB
LATB
0CFh
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
INITIALIZING PORTB
Preliminary
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur. Any RB<7:4>
pins that are configured as outputs are excluded from
the interrupt-on-change comparison.
Comparisons with the input pins (of RB<7:4>) are
made with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are ORed
together to generate the RB Port Change Interrupt with
Flag bit, RBIF (INTCON<0>).
This
power-managed modes. To clear the interrupt in the
Interrupt Service Routine:
1.
2.
3.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after a one T
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB<3:2> pins are multiplexed as CTMU edge
inputs. RB5 has an additional function for Timer3 and
Timer1. It can be configured for Timer3 clock input or
Timer1 external clock gate input.
Perform any read or write of PORTB (except
with the MOVFF (ANY) , PORTB instruction).
Wait one instruction cycle (such as executing a
NOP instruction).
This ends the mismatch condition.
Clear flag bit, RBIF.
interrupt
can
 2011 Microchip Technology Inc.
wake
the
device
CY
delay.
from