PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 262

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
19.1
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
19.1.1
The CCP modules utilize Timers, 1 through 4, varying
with the selected mode. Various timers are available to
the CCP modules in Capture, Compare or PWM
modes, as shown in
TABLE 19-2:
19.1.2
When operating in Output mode (the Compare or PWM
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
DS39977C-page 262
C2TSEL
0
1
CCP Module Configuration
Compare
Capture/
CCP2
CCP MODULES AND TIMER
RESOURCES
OPEN-DRAIN OUTPUT OPTION
TMR1
TMR3
Mode
TIMER ASSIGNMENTS FOR CCP MODULES 2, 3, 4 AND 5
Table
TMR2
TMR4
Mode
PWM
19-1.
C3TSEL
0
1
Compare
Capture/
CCP3
TMR1
TMR3
Mode
CCPTMRS Register
Preliminary
TMR2
TMR4
Mode
PWM
C4TSEL
TABLE 19-1:
The assignment of a particular timer to a module is
determined by the Timer to CCP enable bits in the
CCPTMRS register (see
modules may be active at once and may share the
same timer resource if they are configured to operate
in the same mode (Capture/Compare or PWM) at the
same time.
The CCPTMRS register selects the timers for CCP
modules, 2, 3, 4 and 5. The possible configurations are
shown in
The open-drain output option is controlled by the
CCPxOD bits (ODCON<6:2>). Setting the appropriate
bit configures the pin for the corresponding module for
open-drain operation.
0
1
CCP Mode
Compare
Capture
PWM
Compare
Capture/
CCP4
TMR1
TMR3
Mode
Table
19-2.
CCP MODE – TIMER
RESOURCE
Mode
TMR2
TMR4
PWM
 2011 Microchip Technology Inc.
Timer1 or Timer3
Timer2 or Timer4
Timer Resource
C5TSEL
Register
0 0
0 1
19-2). All of the
Compare
Capture/
CCP5
TMR1
TMR3
Mode
Mode
TMR2
TMR4
PWM