PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 276

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
20.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the ECCP1 pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
The action on the pin is based on the value of the mode
select bits (CCP1M<3:0>). At the same time, the
interrupt flag bit, CCP1IF, is set.
20.3.1
Users must configure the ECCP1 pin as an output by
clearing the appropriate TRIS bit.
FIGURE 20-2:
DS39977C-page 276
latch)
Note:
Compare Mode
ECCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the
(depending on device configuration) to the
default low level. This is not the port I/O
data latch.
0
1
ECCP1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR1H
TMR1H
TMR3H
C1TSEL0
C1TSEL1
C1TSEL2
Comparator
compare
CCPR1L
TMR1L
TMR3L
output
Compare
Match
latch
Preliminary
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
20.3.2
Timer1, 2, 3 or 4 must be running in Timer mode or
Synchronized Counter mode if the ECCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
20.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010 ), the ECCP1 pin is not affected;
only the CCP1IF interrupt flag is affected.
20.3.4
The ECCP module is equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCP1M<3:0> = 1011 ).
The Special Event Trigger resets the Timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPR1 registers to
serve as a programmable Period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D Converter must
already be enabled.
Special Event Trigger
CCP1CON<3:0>
Compare
Output
Logic
4
TIMER1/2/3/4 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
Q
 2011 Microchip Technology Inc.
Output Enable
Event
TRIS
ECCP1 Pin
Trigger
mode