PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 403

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 27-4:
 2011 Microchip Technology Inc.
Mode 0
Mode 1
Mode 2
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
Mode 0:
RXB0OVFL: Receive Buffer 0 Overflow bit
1 = Receive Buffer 0 has overflowed
0 = Receive Buffer 0 has not overflowed
Mode 1:
Unimplemented: Read as ‘ 0 ’
Mode 2:
FIFOEMPTY: FIFO Not Empty bit
1 = Receive FIFO is not empty
0 = Receive FIFO is empty
Mode 0:
RXB1OVFL: Receive Buffer 1 Overflow bit
1 = Receive Buffer 1 has overflowed
0 = Receive Buffer 1 has not overflowed
Mode 1, 2:
RXBnOVFL: Receive Buffer n Overflow bit
1 = Receive Buffer n has overflowed
0 = Receive Buffer n has not overflowed
TXBO: Transmitter Bus-Off bit
1 = Transmit error counter > 255
0 = Transmit error counter  255
TXBP: Transmitter Bus Passive bit
1 = Transmit error counter > 127
0 = Transmit error counter  127
RXBP: Receiver Bus Passive bit
1 = Receive error counter > 127
0 = Receive error counter  127
TXWARN: Transmitter Warning bit
1 = Transmit error counter > 95
0 = Transmit error counter  95
RXWARN: Receiver Warning bit
1 = 127  Receive error counter > 95
0 = Receive error counter  95
EWARN: Error Warning bit
This bit is a flag of the RXWARN and TXWARN bits.
1 = The RXWARN or the TXWARN bits are set
0 = Neither the RXWARN or the TXWARN bits are set
FIFOEMPTY RXBnOVFL
RXB0OVFL RXB1OVFL
R/C-0
R/C-0
R/C-0
—
COMSTAT: COMMUNICATION STATUS REGISTER
RXBnOVFL
R/C-0
R/C-0
R/C-0
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
TXBO
TXBO
TXB0
R-0
R-0
R-0
Preliminary
TXBP
TXBP
TXBP
R-0
R-0
R-0
PIC18F66K80 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RXBP
RXBP
RXBP
R-0
R-0
R-0
TXWARN
TXWARN
TXWARN
R-0
R-0
R-0
x = Bit is unknown
RXWARN
RXWARN
RXWARN
R-0
R-0
R-0
DS39977C-page 403
EWARN
EWARN
EWARN
R-0
R-0
R-0
bit 0