PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 514

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
MULLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39977C-page 514
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
PRODH
PRODL
W
PRODH
PRODL
Q1
literal ‘k’
Multiply Literal with W
MULLW
0  k  255
(W) x k  PRODH:PRODL
None
An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
1
1
MULLW
Read
0000
Q2
=
=
=
=
=
=
E2h
?
?
E2h
ADh
08h
k
0C4h
1101
Process
Data
Q3
kkkk
PRODH:
registers
PRODL
Write
Q4
kkkk
Preliminary
MULWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
PRODH
PRODL
W
REG
PRODH
PRODL
Q1
Multiply W with f
MULWF
0  f  255
a  [0,1]
(W) x (f)  PRODH:PRODL
None
An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
If ‘a’ is ‘ 0 ’, the Access Bank is selected. If
‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f  95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1
register ‘f’
0000
MULWF
Read
Q2
=
=
=
=
=
=
=
=
 2011 Microchip Technology Inc.
f {,a}
C4h
B5h
?
?
C4h
B5h
8Ah
94h
001a
REG, 1
Process
Data
Q3
for details.
ffff
registers
PRODH:
PRODL
Write
Q4
ffff