MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 111

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

5.3.4.1 System Configuration Options Register
M68HC11K Family
MOTOROLA
NOTE:
Address: $0030
The clock monitor function is enabled or disabled by the CME control bit
in the OPTION register (see
overrides CME and enables the clock monitor until the next reset.
In normal operating modes, these bits can be written only once within 64
bus cycles after reset.
CME — Clock Monitor Enable Bit
FCME — Force Clock Monitor Enable Bit
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E-clock frequency below 10 kHz
generates a clock monitor error. An E-clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E clock is below 200 kHz is not recommended.
Reset:
Read:
Write:
Figure 5-4. System Configuration Options Register (OPTION)
This control bit can be read or written at any time and controls whether
or not the internal clock monitor circuit triggers a reset sequence when
the system clock is slow or absent. When it is clear, the clock monitor
circuit is disabled. When it is set, the clock monitor circuit is enabled.
Reset clears the CME bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Clock monitor disabled
1 = Clock monitor enabled
0 = Clock monitor follows the state of the CME bit.
1 = Clock monitor is enabled until the next reset.
ADPU
Bit 7
0
Go to: www.freescale.com
Resets and Interrupts
CSEL
6
0
IRQE
5
0
Figure
DLY
4
1
5-4). The FCME bit in OPTION
CME
3
0
FCME
2
0
Resets and Interrupts
Sources of Resets
CR1
1
0
Technical Data
Bit 0
CR0
0
111