MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 145

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

6.9 Port G
M68HC11K Family
MOTOROLA
Alternate Pin Function:
1. Not available on KS devices
1. Not available on KS devices
Address: $007E
Address: $007F
The state of port G pin 7 (PG7) at reset is mode dependent. In
single-chip or bootstrap modes, it is a high-impedance input; its data
direction can be changed through DDRG. In expanded and special test
modes, PG7 functions as the R/W line to control the direction of data flow
between the MCU and external memory devices.
Port G pins (PG[6:0]) reset to high-impedance inputs in any mode. Data
direction can be changed through DDRG. Port G bits [5:0] can serve as
memory expansion address lines (see
expanded and special test modes. M68HC11KS devices do not contain
these pins.
All eight port G pins have selectable internal pullup resistors (see
Internal Pullup
DDG[7:0] — Data Direction for Port G Bits
Reset:
Reset:
Read:
Read:
Write:
Write:
Freescale Semiconductor, Inc.
Figure 6-14. Port G Data Direction Register (DDRG)
For More Information On This Product,
0 = Input
1 = Output
Figure 6-13. Port G Data Register (PORTG)
DDG7
Bit 7
PG7
R/W
Bit 7
0
0
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Parallel Input/Output
DDG6
PG6
Resistors).
—
6
0
6
0
(1)
(1)
DDG5
PG5
XA18
5
0
5
0
(1)
(1)
DDG4
PG4
XA17
4
0
4
0
(1)
(1)
11.3 Memory
DDG3
PG3
XA16
3
0
3
0
(1)
(1)
DDG2
PG2
XA15
2
0
2
0
(1)
(1)
Expansion) in
Parallel Input/Output
DDG1
PG1
XA14
1
0
1
0
Technical Data
(1)
(1)
DDG0
PG0
XA13
6.11
Bit 0
Bit 0
Port G
0
0
(1)
145
(1)