MC68HC711KS2CFN3 Freescale Semiconductor, MC68HC711KS2CFN3 Datasheet - Page 113

• Manufacturer Part Number: MC68HC711KS2CFN3
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC711KS2CFN3

• Cpu Family: HC11
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI/SPI
• Program Memory Type: ROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 51
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

M68HC11K Family
MOTOROLA
NOTE:
NOTE:
STRCH is cleared on reset; therefore, a program cannot execute out of
reset in a slow external ROM.
STRCH is not available on M68HC11K devices.
IRVNE — Internal Read Visibility/Not E Bit
Single-chip
Expanded
Bootstrap
Special test
To use the STRCH feature, ROMON must be set on reset so that the
device starts with internal ROM included in the memory map. STRCH
should then be set.
STRCH has no effect in single-chip and bootstrap modes.
IRVNE can be written once in any user mode. In expanded modes,
IRVNE determines whether IRV is on or off (but has no meaning in
user expanded secure mode, as IRV must be disabled). In special test
mode, IRVNE is reset to 1. In normal modes, IRVNE is reset to 0.
In single-chip modes, this bit determines whether the E clock drives
out from the chip.
Refer to
following reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
Mode
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus
1 = E pin is driven low.
0 = E clock is driven out from the chip.
Table 5-3
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Table 5-3. IRVNE Operation After Reset
Resets and Interrupts
IRVNE
Reset
after
0
0
0
1
for a summary of the operation immediately
E Clock
Reset
after
On
On
On
On
Reset
after
IRV
Off
Off
Off
On
Affects
IRVNE
Only
IRV
IRV
E
E
Resets and Interrupts
Sources of Resets
Technical Data
Unlimited
Unlimited
Can Be
Written
IRVNE
Once
Once
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