ACS8520T Semtech, ACS8520T Datasheet - Page 11

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Direct Lock Mode 155 MHz.
The max frequency allowed for phase comparison is
77.76MHz, so for the special case of a 155 MHz input set
to Direct Lock Mode, there is a divide-by-two function
automatically selected to bring the frequency down to
within the limits of operation.
Table 4 Input Reference Source Selection and Priority Table
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Port Number
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
(ii) To achieve 8 kHz, the 10 MHz input must be
frequency to 8 kHz, the post-division frequency.
(XX = “Leaky Bucket” ID for this input).
divided by 1,250. So, if DivN, = 250 = (N+1)
then N must be set to 1,249. This is done by
writing 4E1 hex (1,249 decimal) to the DivN
register pair Reg. 46/47.
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Number (Bin)
Channel
AMI
AMI
TTL/CMOS
TTL/CMOS
LVDS/PECL LVDS
default
PECL/LVDS PECL
default
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
Technology
Input Port
64/8 kHz (composite clock, 64 kHz + 8 kHz)
Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz
64/8 kHz (composite clock, 64 kHz + 8 kHz)
Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 155.52 MHz (see Note (ii))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
Up to 100 MHz (see Note (i)) Default (Master) (SONET): 1.544 MHz Default
(Master) (SDH): 2.048 MHz Default (Slave) 6.48 MHz
Up to 100 MHz (see Note (i))
Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz
FINAL
Page 11
PECL/LVDS/AMI Input Port Selection
The choice of PECL or LVDS compatibility is programmed
via the cnfg_differential_inputs register. Unused PECL
differential inputs should be fixed with one input High
(VDD) and the other input Low (GND), or set in LVDS mode
and left floating, in which case one input is internally
pulled High and the other Low.
An AMI port supports a composite clock, consisting of a
64 kHz AMI clock with 8 kHz boundaries marked by
deliberate violations of the AMI coding rules, as specified
in ITU recommendation G.703
nominal pattern are detected within the ACS8520, and
may cause reference-switching if too frequent. See
section DC Characteristics: AMI Input/Output Port, for
more details. If the AMI port is unused, the pins (I1 and I2)
should be tied to GND.
Frequencies Supported
ACS8520 SETS
[6]
. Departures from the
DATASHEET
www.semtech.com
2
3
4
5
6
7
8
9
10
11
12/1 (Note
(iii))
13
Default
Priority