ACS8520T Semtech, ACS8520T Datasheet - Page 123

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
fine_limit_en
Register Name
coarse_lim-
phaseloss_en
Bit No.
Bit No.
Bit 7
[4:3]
[2:0]
Bit 7
5
7
73 (cont...)
74
cnfg_phase_loss_fine_limit
noact_ph_loss
Description
narrow_en (test control bit)
Set to 1 (default value)
Not used.
phase_loss_fine_limit
When enabled by Bit 7, this register coarsely sets
the phase limit at which the device indicates phase
lost or locked. The default value of 2 (010) gives a
window size of around ±(90º to 180º). The phase
position of the inputs to the DPLL has to be within
the window limit for 1 to 2 seconds before the
device indicates phase lock. If it is outside the
window for any time then phase loss is immediately
indicated. For most cases the default value of 2
(010) is satisfactory. The window size changes in
proportion to the value, so a value of 1 (001) will
give a narrow phase acceptance or lock window of
approximately ±(45º to 90º).
cnfg_phase_loss_coarse_limit
wide_range_en multi_ph_resp
Description
coarse_lim_phaseloss_en
Register bit to enable the coarse phase detector,
whose range is determined by
phase_loss_coarse_limit Bits [3:0]. This register
sets the limit in the number of input clock cycles (UI)
that the input phase can move by before the DPLL
indicates phase lost.
Bit 6
Bit 6
narrow_en
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 123
(R/W) Register to configure some
of the parameters of the T0 DPLL
phase detector.
(R/W) Register to configure some
of the parameters of the T0 DPLL
phase detector.
Bit Value
Bit Value
Bit 3
Bit 3
000
001
010
011
100
101
110
111
0
1
0
1
-
Value Description
Set to 1
-
Do not use. Indicates phase loss continuously.
Small phase window for phase lock indication.
Recommended value.
)
)
) Larger phase window for phase lock indication.
)
)
Value Description
Phase loss not triggered by the coarse phase lock
detector.
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_coarse_limit,
Bits [3:0].
phase_loss_coarse_limit
Bit 2
Bit 2
phase_loss_fine_limit
Default Value
Default Value
ACS8520 SETS
Bit 1
Bit 1
DATASHEET
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1010 0010
1000 0101
Bit 0
Bit 0