ACS8520T Semtech, ACS8520T Datasheet - Page 58

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
phase_alarm
Bit No.
Bit 7
7
6
5
4
3
2
1
0
03
test_register1
disable_180
Description
phase_alarm (phase alarm (R/O))
Instantaneous result from T0 DPLL
disable_180
Normally the DPLL will try to lock to the nearest
edge (±180°) for the first 2 seconds when locking to
a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ±360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to 2
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
Not used.
resync_analog (analog dividers re-synchronization)
The analog output dividers include a
synchronization mechanism to ensure phase lock at
low frequencies between the input and the output.
Test Control
Leave unchanged or set to 0
8k Edge Polarity
When lock 8k mode is selected for the current input
reference source, this bit allows the system to lock
on either the rising or the falling edge of the input
clock.
Test Control
Leave unchanged or set to zero
Test Control
Leave unchanged or set to zero
Bit 6
Bit 5
Description
resync_analog
Bit 4
FINAL
Page 58
(R/W) Register containing various
test controls (not normally used).
Set to zero
Bit Value
Bit 3
0
1
0
1
0
1
0
0
1
0
0
-
8k Edge Polarity Set to zero
Value Description
T0 DPLL reporting phase locked.
T0 DPLL reporting phase lost.
T0 DPLL automatically determines frequency lock
enable.
T0 DPLL forced to always frequency and phase lock.
-
Analog divider only synchronized during first 2
seconds after power-up.
Analog dividers always synchronized.This keeps the
clocks divided down from the APLL output, in sync
with equivalent frequency digital clocks in the DPLL.
Hence ensuring that 6.48 MHz output clocks, and
above, are in sync with the DPLL even though only a
77.76 MHz clock drives the APLL.
-
Lock to falling clock edge.
Lock to rising clock edge.
-
-
Bit 2
Default Value
ACS8520 SETS
Bit 1
DATASHEET
www.semtech.com
0001 0100
Set to zero
Bit 0