ACS8520T Semtech, ACS8520T Datasheet - Page 113

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Bit No.
Bit 7
[2:0]
7
6
5
4
3
64
cnfg_T4_DPLL_frequency
Auto_squelch_
T4
Description
Not used.
Auto_squelch_T4
Register bit to automatically squelch the T4 outputs
on TO8 and TO9 when the T4 inputs have failed.
AMI_op_duty
Register bit to configure whether the composite
clock output of TO8 is 50:50 or 5:8 duty cycle.
T4_op_SONSDH
Register bit to configure the BITS output on TO9 to
be either SONET or SDH frequency, only when
Reg. 35 Bit 4 = 0, otherwise this bit is ignored and
SONET/SDH selection for TO9 is controlled by
Reg. 34 Bit 2.
Default set by SONSDHB pin - same as Reg. 34 Bit
2.
Not used.
T4_DPLL_frequency
Register to configure the frequency of operation of
the DPLL in the T4 path. The frequency of the DPLL
will also affect the frequency of the T4 APLL which,
in turn, affects the frequencies available at outputs
TO1 - TO7 see Reg. 60 - Reg. 63. It is also possible
to not use the T4 DPLL at all, but use the T4 APLL to
run directly from the T0 DPLL output, see Reg. 65
(cnfg_TO_DPLL_frequency). If any frequencies are
required from the T4 APLL then the T4 DPLL should
not be squelched, as the T4 APLL input is squelched
and the T4 APLL will free run.
Bit 6
AMI_op_duty
Bit 5
Description
T4_op_
SONSDH
Bit 4
FINAL
Page 113
(R/W) Register to configure the T4
DPLL and several other
parameters for the T4 path.
Bit Value
Bit 3
000
001
010
011
100
101
110
111
0
1
0
1
0
1
-
-
Value Description
-
Outputs TO8 and TO9 enabled as in Reg. 63.
Outputs TO8 and TO9 disabled when T4 inputs fail.
TO8 output 50:50 duty cycle.
TO8 output 5:8 duty cycle.
TO9 output 2.048 MHz (SDH).
TO9 output 1.544 MHz (SONET).
-
T4 DPLL mode = squelched (clock off).
T4 DPLL mode = 77.76 MHz (OC-N rates), giving
T4 APLL output frequency (before dividers) =
311.04 MHz.
T4 DPLL mode = 12E1, giving T4 APLL output
frequency (before dividers) = 98.304 MHz.
T4 DPLL mode = 16E1, giving T4 APLL output
frequency (before dividers) = 131.072 MHz.
T4 DPLL mode = 24DS1, giving T4 APLL output
frequency (before dividers) = 148.224 MHz.
T4 DPLL mode = 16DS1, giving T4 APLL output
frequency (before dividers) = 98.816 MHz.
T4 DPLL mode = E3, giving T4 APLL output
frequency (before dividers) = 274.944 MHz.
T4 DPLL mode = DS3, giving T4 APLL output
frequency (before dividers) = 178.944 MHz.
Bit 2
T4_DPLL_frequency
Default Value
ACS8520 SETS
Bit 1
DATASHEET
www.semtech.com
0000 0001
Bit 0