ACS8520T Semtech, ACS8520T Datasheet - Page 96

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
freq_mon_clk
Bit No.
Bit No.
Bit 7
[5:0]
Bit 7
7
6
5
47 (cont...)
48
cnfg_freq_divn
[13:8]
Description
divn_value[13:8]
This register, in conjunction with Reg. 46
(cnfg_freq_divn) represents the integer value by
which to divide inputs that use the DivN pre-divider.
The divn feature supports input frequencies up to a
maximum of 100 MHz; therefore, the maximum
value that should be written to this register is 30D3
hex (12499 dec). Use of higher DivN values may
result in unreliable behavior.
cnfg_monitors
los_flag_on_
TDO
Description
freq_mon_clk
Bit to select the source of the clock to the frequency
monitors to be either from the output clock or
directly from the crystal oscillator.
los_flag_on_TDO
Bit to select whether the main_ref_fail interrupt
from the T0 DPLL is flagged on the TDO pin. If
enabled this will not strictly conform to the IEEE
1149.1 JTAG standard for the function of the TDO
pin. When enabled the TDO pin will simply mimic the
state of the main_ref_fail interrupt status bit.
ultra_fast_switch
Bit to enable ultra-fast switching mode. When in this
mode, the device will disqualify a locked-to source
as soon as it detects a few missing input cycles.
Bit 6
Bit 6
ultra_fast_
switch
Bit 5
Bit 5
Description
Description
ext_switch
Bit 4
Bit 4
FINAL
Page 96
(R/W) Bits [13:8] of the division
factor for inputs using the DivN
feature.
(R/W) Configuration register
controlling several input
monitoring and switching options.
PBO_freeze
Bit Value
Bit Value
Bit 3
Bit 3
0
1
0
1
0
1
-
divn_value[13:8]
Value Description
The input frequency will be divided by the value in
this register plus 1. i.e. to divide by 8, program a
value of 7.
PBO_en
Value Description
Frequency monitors clocked by output of TO DPLL.
Frequency monitors clocked by crystal oscillator
frequency.
Normal mode, TDO complies with IEEE 1149.1.
TDO pin used to indicate the state of the
main_ref_fail interrupt status. This allows a system
to have a hardware indication of a source failure
very rapidly.
Currently selected source only disqualified by Leaky
Bucket or frequency monitors.
Currently selected source disqualified after less
than 3 missing input cycles.
Bit 2
Bit 2
Default Value
Default Value
freq_monitor_
soft_enable
ACS8520 SETS
Bit 1
Bit 1
DATASHEET
www.semtech.com
0011 1111
0000 0101*
freq_monitor_
hard_enable
Bit 0
Bit 0