ACS8520T Semtech, ACS8520T Datasheet - Page 120

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
T0_PD2_gain_
enable
Register Name
Bit No.
Bit No.
Bit 7
[2:0]
Bit 7
[7:0]
6D (cont...)
70
cnfg_T0_DPLL_PD2_gain
Description
T0_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. This setting is always used if automatic gain
selection is disabled in Bit 7, T0_PD2_gain_enable.
cnfg_phase_offset
[7:0]
Description
phase_offset_value[7:0]
Register forming part of the phase offset control.
Bit 6
Bit 6
T0_PD2_gain_alog
Bit 5
Bit 5
Description
Description
phase_offset_value[7:0]
Bit 4
Bit 4
FINAL
Page 120
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for the T0 DPLL.
(R/W) Bits [7:0] of the phase
offset control register.
Bit Value
Bit Value
Bit 3
Bit 3
-
-
Value Description
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Value Description
See Reg. 71, cnfg_phase_offset[15:8] for more
details.
Bit 2
Bit 2
T0_PD2_gain_digital
Default Value
Default Value
ACS8520 SETS
Bit 1
Bit 1
DATASHEET
www.semtech.com
1100 0010
0000 0000
Bit 0
Bit 0