ACS8520T Semtech, ACS8520T Datasheet - Page 20

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

of the output signals from the DPLL is one 204.8 MHz
cycle or 4.9 ns.
Additional resolution and lower final output jitter is
provided by a de-jittering Analog PLL that reduces the
4.9 ns p-p jitter from the digital down to 500 ps p-p and
60 ps RMS as typical final outputs measured broadband
(from 10 Hz to 1 GHz).
This arrangement combines the advantages of the
flexibility and repeatability of a DPLL with the low jitter of
an APLL. The DPLLs in the ACS8520 are uniquely very
programmable for all PLL parameters of bandwidth (from
0.1 Hz up to 70 Hz), damping factor (from 1.2 to 20),
frequency acceptance and output range (from 0 to
80 ppm, typically 9.2 ppm), input frequency (12 common
SONET/SDH spot frequencies) and input-to-output phase
offset (in 6 ps steps up to 200 ns). There is no
requirement to understand the loop filter equations or
detailed gain parameters since all high level factors such
as overall bandwidth can be set directly via registers in
the microprocessor interface. No external critical
components are required for either the internal DPLLs or
APLLs, providing another key advantage over traditional
discrete designs.
The T4 DPLL is similar in structure to the T0 DPLL, but
since the T4 is only providing a clock synthesis and input
to output frequency translation function, with no defined
requirement for jitter attenuation or input phase jump
absorption, then its bandwidth is limited to the high end
and the T4 does not incorporate many of the Phase Build-
out and adjustment facilities of the T0 DPLL.
TO DPLL Main Features
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Two programmable DPLL bandwidth controls (Locked
and Acquisition bandwidth), each with 10 steps from
0.1 Hz to 70 Hz
Programmable damping factor: For optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
Multiple phase lock detectors
Input to output phase offset adjustment
(Master/Slave), ±200 ns, 6 ps resolution step size
PBO phase offset on source switching - disturbance
down to ±5 ns
Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
FINAL
Page 20
T4 DPLL Main Features
The structure of the T0 and T4 PLLs are shown later in
Figure 11 in the section on output clock ports. That
section also details how the DPLLs and particular output
frequencies are configured. The following sections detail
some component parts of the DPLL.
TO DPLL Automatic Bandwidth Controls
In Automatic Bandwidth Selection mode (Reg. 3B Bit 7),
the T0 DPLL bandwidth setting is selected automatically
from the Acquisition Bandwidth or Locked Bandwidth
configurations programmed in cnfg_T0_DPLL_acq_bw
Reg. 69 and cnfg_T0_DPLL_locked_bw Reg. 67
respectively. If this mode is not selected, the DPLL
acquires and locks using only the bandwidth set by .
Holdover frequency averaging with a choice of
averaging times: 8 minutes or 110 minutes and value
can be read out
Multiple E1 and DS1 outputs supported
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
A single programmable DPLL bandwidth control:
18 Hz, 35 Hz, or 70 Hz
Programmable damping factor: For optional faster
locking and peaking control. Factors = 1.2, 2.5, 5, 10
or 20
Multiple phase lock detectors
Multi-cycle phase detection and locking,
programmable up to ±8192 UI - improves jitter
tolerance in direct lock mode
DS3/E3 support (44.736 MHz / 34.368 MHz) at same
time as OC-N rates from T0
Low jitter E1/DS1 options at same time as OC-N rates
from T0
Frequencies of n x E1/DS1 including 16 and 12 x E1,
and 16 and 24 x DS1 supported
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
Can use the T4 DPLL as an Independent FrSync DPLL
Can use the phase detector in T4 DPLL to measure
the input phase difference between two inputs.
ACS8520 SETS
DATASHEET
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