ACS8520T Semtech, ACS8520T Datasheet - Page 129

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
ph_offset_ramp
indep_FrSync/
MFrSync
Bit No.
Bit No.
Bit 7
[1:0]
Bit 7
[6:4]
7
7B (cont...)
7C
cnfg_sync_phase
Description
Sync_phase
Register to control the sampling of the external Sync
input. Nominally the falling edge of the input is
aligned with the falling edge of the reference clock.
The margin is ±0.5 U.I. (Unit Interval).
cnfg_sync_monitor
Description
ph_offset_ramp
Register bit to force an internal phase offset
calibration, see Reg. 71, Cnfg_Phase_Offset.
The calibration routine is transparent to the outside
and puts the device in holdover while it internally
ramps the phase offset to zero, resets all internal
output and feedback dividers and then ramps the
phase offset to the current programmed value from
Reg. 70 or 71., holdover is then turned off. All this is
transparent to the outside with no change in output
phase offset visible.
Sync_monitor_limit
An alternative to allowing the external Sync input to
synchronize the outputs, is to use the Sync monitor
block to alarm when the external Sync input does
not align with the output within a certain number of
input clock cycles. This register defines the limit in
UI of the selected reference source. If the alignment
does not occur within this limit, then Sync alarm will
be raised, see Reg. 09 Bit 7.
Sync_OC-N_
rates
Bit 6
Bit 6
Sync_monitor_limit
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 129
(R/W) Register to configure the
behavior of the synchronization
for the external frame reference.
(R/W) Register to configure the
external Sync input monitor. It
also has a bit to control the phase
offset automatic ramping feature.
Bit Value
Bit Value
Bit 3
Bit 3
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Value Description
On target.
0.5 U.I. early
1 U.I. late
0.5 U.I. late.
Value Description
Phase offset automatically ramped from the old
value to the new value when there is a change in
Reg. 70 or 71.
Start phase offset internal calibration routine. This
bit is reset to 0 when this is complete.
Sync alarm raised beyond ±1 UI.
Sync alarm raised beyond ±2 UI.
Sync alarm raised beyond ±3 UI.
Sync alarm raised beyond ±4 UI.
Sync alarm raised beyond ±5 UI.
Sync alarm raised beyond ±6 UI.
Sync alarm raised beyond ±7 UI.
Sync alarm raised beyond ±8 UI.
Sync_reference_source
Bit 2
Bit 2
Default Value
Sync_phase
Default Value
ACS8520 SETS
Bit 1
Bit 1
DATASHEET
www.semtech.com
0000 0000
0010 1011
Bit 0
Bit 0