ACS8520T Semtech, ACS8520T Datasheet - Page 23

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Output Wander
Wander and jitter present on the output clocks are
dependent on:
Wander and jitter are treated in different ways to reflect
their differing impacts on network design. Jitter is always
strongly attenuated, whilst wander attenuation can be
varied to suit the application and operating state. Wander
and jitter attenuation is performed using a digital phase
locked loop (DPLL) with a programmable bandwidth. This
gives a transfer characteristic of a low pass filter, with a
programmable pole. It is sometimes necessary to change
the filter dynamics to suit particular circumstances - one
example being when locking to a new source, the filter can
be opened up to reduce locking time and can then be
tightened again to remove wander. A change between
different bandwidths for locking and for acquisition is
handled automatically within the ACS8520.
There may be a phase shift across the ACS8520 between
the selected input reference source and the output clock
over time, mainly caused by frequency wander in the
external oscillator module. Higher stability XOs will give
better performance for MTIE. The oscillator becomes
more critical at DPLL bandwidth near to or below 0.1 Hz
since the rate of change of the DPLL may be slow
compared to the rate of change of the oscillator
frequency. Shielding of the OCXO or TCXO can further slow
down the rate of change of temperature and hence
frequency, thus improving output wander performance.
The phase shift may vary over time but will be constrained
to lie within specified limits. The phase shift is
characterized using two parameters, MTIE (Maximum
Time Interval Error) and TDEV (Time Deviation) which,
although being specified in all relevant specifications,
differ in acceptable limits in each one.
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
The magnitudes of wander and jitter on the selected
input reference clock (in Locked mode)
The internal wander and jitter transfer characteristic
(in Locked mode)
The jitter on the local oscillator clock
The wander on the local oscillator clock (in Holdover
mode).
FINAL
Page 23
Typical measurements for the ACS8520 are shown in
Figure 6, for Locked mode operation. Figure 7 shows a
typical measurement of Phase Error accumulation in
Holdover mode operation.
The required performance for phase variation during
Holdover is specified in several ways and depends on the
relevant specification (See “References” on page 146),
for example:
1. ETSI ETS-300 462-5
2. ETSI ETS-300 462-5
3. ANSI Tin1.101-1999
4. Telcordia GR-1244-CORE
5. ITU G.822
short-term phase error during switchover (i.e. Locked
to Holdover to Locked) be limited to an accumulation
rate no greater than 0.05 ppm during a 15 second
interval.
long-term phase error in the Holdover mode should
not exceed
{(a1 + a2)S + 0.5bS
where
a1 = 50 ns/s (allowance for initial frequency offset)
a2 = 2000 ns/s (allowance for temperature variation)
b = 1.16x10
c = 120 ns (allowance for entry into Holdover mode).
S = Elapsed time (s) after loss of external ref. input
the phase variation be limited so that no more than
255 slips (of 125 µs each) occur during the first day of
Holdover. This requires a frequency accuracy better
than:
((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm
Temperature variation is not restricted, except to
within the normal bounds of 0 to 50°C.
an initial frequency offset of 50 ppb is permitted on
entering Holdover, whilst a drift over temperature of
280 ppb is allowed; an allowance of 40 ppb is
permitted for all other effects.
during category (b) operation (interpreted as being
applicable to Holdover mode operation) be limited to
less than 30 slips (of 125 µs each) per hour.
((60 x 60) + (30 x 125 µs))/(60 x 60)) = 1.042 ppm
[12]
-4
, Section 2.6, requires that the slip rate
ns/s
2
2
[4]
[4]
(allowance for ageing)
[1]
+ c}
, Section 9.1, requires that the
, Section 9.2, requires that the
, Section 8.2.2, requires that
[19]
ACS8520 SETS
, Section 5.2, shows that
DATASHEET
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