ACS8520T Semtech, ACS8520T Datasheet - Page 122

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
fine_limit_en
Bit No.
Bit No.
Bit 7
[7:6]
[5:0]
Bit 7
7
6
72
73
cnfg_PBO_phase_offset
Description
Not used.
PBO_phase_offset
Each time a Phase Build-out event is triggered,
there is an uncertainty of up to 5 ns introduced
which translates to a phase hit on the output. The
mean error over a large number of events is
designed to be zero. This register can be used to
introduce a fixed offset into each PBO event. This
will have the effect of moving the mean error
positive or negative in time.
cnfg_phase_loss_fine_limit
noact_ph_loss
Description
fine_limit_en
Register bit to enable the phase_loss_fine_limit
Bits [2:0]. When disabled, phase lock/loss is
determined by the other means within the device.
This must be disabled when multi-UI jitter tolerance
is required, see Reg. 74,
cnfg_phase_loss_course_limit.
noact_ph_loss
The DPLL detects that an input has failed very
rapidly. Normally, when the DPLL detects this
condition, it does not consider phase lock to be lost
and will phase lock to the nearest edge (±180º)
when a source becomes available again, hence
giving tolerance to missing cycles. If phase loss is
indicated, then frequency and phase locking is
instigated (±360º locking). This bit can be used to
force the DPLL to indicate phase loss immediately
when no activity is detected.
Bit 6
Bit 6
narrow_en
Bit 5
Bit 5
Description
Description
Bit 4
Bit 4
FINAL
Page 122
(R/W) Register to offset the mean
time error of Phase Build-out
events.
(R/W) Register to configure some
of the parameters of the T0 DPLL
phase detector.
Bit Value
Bit Value
Bit 3
Bit 3
0
1
0
1
PBO_phase_offset
-
-
Value Description
-
The value in this register is a 6-bit 2’s complement
number. The value multiplied by 0.101 gives the
programmed offset in nanoseconds. Values greater
than +1.4 ns or less than -1.4 ns should NOT be
used as they may cause internal mathematical
errors.
Value Description
Phase loss indication only triggered by other means.
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_fine_limit,
Bits [2:0].
No activity on reference does not trigger phase lost
indication.
No activity triggers phase lost indication.
Bit 2
Bit 2
phase_loss_fine_limit
Default Value
Default Value
ACS8520 SETS
Bit 1
Bit 1
DATASHEET
www.semtech.com
0000 0000
1010 0010
Bit 0
Bit 0