ACS8520T Semtech, ACS8520T Datasheet - Page 16

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

The mode is initialized by either holding SRCSW pin High
during reset (SRCSW must remain High for at least a
further 251 ms after PORB has gone High - see following
Note), or by writing to Reg. 48 Bit 4. After External
Protection Switching mode has been initialized, the value
on this pin directly selects either I3/I5 (SRCSW High) or
I4/I6 (SRCSW Low). If this mode is initialized at reset by
pulling the SRCSW pin High, then it configures the default
frequency tolerance of I3/I5 and I4/I6 to ±80 ppm
(Reg. 41 and Reg. 42) as opposed to the normal
frequency tolerance of ±9.2 ppm. Any of these registers
can be subsequently set by external software, if required.
Note...The 251 ms comprises 250 ms allowance for the
internal reset to be removed plus 1 ms allowance for APLLs to
start-up and become stable.
Selection of either input I3 or I5 is determined by the
Priority value of I3; if the programmed priority of I3 is 0,
then I5 is selected. Similarly, I6 is selected if the
programmed priority of I4 is 0.
Figure 4 I3/I5 and I4/I6 Switching
When external protection switching is enabled, the device
will operate as a simple switch. All clock monitoring is
disabled and the DPLL will simply be forced to try to lock
on to the indicated reference source. Consequently the
device will always indicate “locked” state in the
sts_operating register (Reg. 09, Bits [2:0]).
Output Clock Phase Continuity on Source
Switchover
If either PBO is selected on (default), or, if DPLL frequency
limit is set to less than ±30 ppm or (±9.2 ppm default), the
device will always comply with GR-1244-CORE
specification for Stratum 3 (maximum rate of phase
change of 81 ns/1.326 ms), for all input frequencies.
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
I4 Priority >0
I3 Priority >0
I3
I5
I4
I6
1
0
1
0
SRCSW
1
0
F8530D_006IPSWI3I4I5I6_01
T0 DPLL
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FINAL
Page 16
Modes of Operation
The ACS8520 has three primary modes of operation
(Free-run, Locked and Holdover) supported by three
secondary, temporary modes (Pre-locked, Lost-phase and
Pre-locked2). These are shown in the State Transition
Diagram for the T0 DPLL, Figure 5.
The ACS8520 can operate in Forced or Automatic control.
On reset, the ACS8520 reverts to Automatic Control,
where transitions between states are controlled
completely automatically. Forced Control can be invoked
by configuration, allowing transitions to be performed
under external control. This is not the normal mode of
operation, but is provided for special occasions such as
testing, or where a high degree of hands-on control is
required.
Free-run Mode
The Free-run mode is typically used following a power-on-
reset or a device reset before network synchronization
has been achieved. In the Free-run mode, the timing and
synchronization signals generated from the ACS8520 are
based on the 12.800 MHz clock frequency provided from
the external oscillator and are not synchronized to an
input reference source. By default, the frequency of the
output clock is a fixed multiple of the frequency of the
external oscillator, and the accuracy of the output clock is
equal to the accuracy of the oscillator. However the
external oscillator frequency can be calibrated to improve
its accuracy by a software calibration routine using
register cnfg_nominal_frequency (Reg. 3C and 3D). For
example a 500 ppm offset crystal could be made to look
like one accurate to within ±0.02 ppm.
The transition from Free-run to Pre-locked occurs when
the ACS8520 selects a reference source.
Pre-locked Mode
The ACS8520 will enter the Locked state in a maximum of
100 seconds, as defined by GR-1244-CORE
specification, if the selected reference source is of good
quality. If the device cannot achieve lock within 100
seconds, it reverts to Free-run mode and another
reference source is selected.
Locked Mode
The Locked mode is entered from Pre-locked, Pre-locked2
or Phase-lost mode when an input reference source has
been selected and the DPLL has locked. The DPLL is
ACS8520 SETS
DATASHEET
www.semtech.com
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