ACS8520T Semtech, ACS8520T Datasheet - Page 92

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
Register Name
Bit No.
Bit No.
Bit 7
[7:0]
Bit 7
[7:2]
[1:0]
41
42
cnfg_DPLL_freq_limit
[7:0]
Description
DPLL_freq_limit_value[7:0]
This register defines the extent of frequency offset
to which either the T0 or the T4 DPLL will track a
source before limiting- i.e. it represents the pull-in
range of the DPLLs. The offset of the device is
determined by the frequency offset of the DPLL
when compared to the offset of the external crystal
oscillator clocking the device. If the oscillator is
calibrated using cnfg_nominal_frequency Reg. 3C
and 3D, then this calibration is automatically taken
into account. The DPLL frequency limit limits the
offset of the DPLL when compared to the calibrated
oscillator frequency.
cnfg_DPLL_freq_limit
[9:8]
Description
Not used.
DPLL_freq_limit_value[9:8]
Bit 6
Bit 6
Bit 5
Bit 5
Description
Description
DPLL_freq_limit_value[7:0]
Bit 4
Bit 4
FINAL
Page 92
(R/W) Bits [7:0] of the DPLL
frequency limit register.
(R/W) Bits [9:8] of the DPLL
frequency limit register.
Bit Value
Bit Value
Bit 3
Bit 3
-
-
-
Value Description
In order to calculate the frequency limit in ppm,
Bits [1:0] of Reg. 42 and Bits [7:0] of Reg. 41 need
to be concatenated. This value is a unsigned integer
and represents limit both positive and negative in
ppm. The value multiplied by 0.078 will give the
value in ppm.
Value Description
-
See Reg. 41 (cnfg_DPLL_freq_limit) for details.
Bit 2
Bit 2
Default Value
Default Value
ACS8520 SETS
DPLL_freq_limit_value[9:8]
Bit 1
Bit 1
DATASHEET
www.semtech.com
0111 0110
0000 0000
Bit 0
Bit 0