ACS8520T Semtech, ACS8520T Datasheet - Page 114

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
T4_meas_T0_
ph
Bit No.
Bit 7
[5:4]
[2:0]
7
6
3
65
cnfg_T0_DPLL_frequency
T4_APLL_for_
T0
Description
T4_meas_T0_ph
Register bit to control the feature to use the T4 path
to measure phase offset from the T0 path. When
enabled the T4 path is disabled and the phase
detector is used to measure the phase between the
input to the T0 DPLL and the selected T4 input.
T4_APLL_for_T0
Register bit to select whether the T4 APLL takes its
input from the T4 DPLL or the T0 DPLL. If the T0
DPLL is selected then the frequency is controlled by
Bits [5:4], T0_freq_to_T4_APLL.
T0_freq_to_T4_APLL
Register to select the T0 frequency driven to the T4
APLL (T0 DPLL mode*) when selected by Bit 6,
T4_APLL_for_T0; and consequently the APLL output
frequency in the T4 path.
*Note that this is not the operating frequency of the
T0 DPLL itself - which is fixed at outputting
77.76 MHz - but is the multiplied output from the LF
Output DFS block. See “PLL Block Diagram” on
page 33.
Not used.
T0_DPLL_frequency
Register to configure the frequency driven to the T0
APLL (T0 DPLL mode*) and consequently the APLL
output frequency in the T0 path. This register
affects the frequencies available at TO1 - TO7 see
Reg. 60 - Reg. 63.
*Note that this is not the operating frequency of the
T0 DPLL itself - which is fixed at outputting
77.76 MHz - but is the multiplied output from the LF
Output DFS block. See “PLL Block Diagram” on
page 33.
Bit 6
Bit 5
T0_freq_to_T4_APLL
Description
Bit 4
FINAL
Page 114
(R/W) Register to configure the T0
DPLL and several other
parameters for the T0 path.
Bit Value
Bit 3
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
-
Value Description
Normal- T4 Path normal operation.
T4 DPLL disabled, T4 phase detector used to
measure phase between selected T0 input and
selected T4 input.
T4 APLL takes its input from the T4 DPLL.
T4 APLL takes its input from the T0 DPLL.
T0 DPLL mode = 12E1, giving T4 APLL output
frequency (before dividers) = 98.304 MHz.
T0 DPLL mode = 16E1, giving T4 APLL output
frequency (before dividers) = 131.072 MHz.
T0 DPLL mode = 24DS1, giving T4 APLL output
frequency (before dividers) = 148.224 MHz.
T0 DPLL mode = 16DS1, giving T4 APLL output
frequency (before dividers) = 98.816 MHz.
-
T0 DPLL mode = 77.76 MHz, digital feedback,
T0 APLL output frequency (before dividers) =
311.04 MHz.
T0 DPLL mode = 77.76 MHz, analog feedback,
T0 APLL output frequency (before dividers) =
311.04 MHz.
T0 DPLL mode = 12E1, giving T0 APLL output
frequency (before dividers) = 98.304 MHz.
T0 DPLL mode = 16E1, giving T0 APLL output
frequency (before dividers) = 131.072 MHz.
T0 DPLL mode = 24DS1, giving T0 APLL output
frequency (before dividers) = 148.224 MHz.
T0 DPLL mode = 16DS1, giving T0 APLL output
frequency (before dividers) = 98.816 MHz.
Not used.
Not used.
Bit 2
T0_DPLL_frequency
Default Value
ACS8520 SETS
Bit 1
DATASHEET
www.semtech.com
0000 0001
Bit 0