ACS8520T Semtech, ACS8520T Datasheet - Page 9

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

VDD5 pin). The AMI inputs are ±1 V typically A.C. coupled.
Refer to the electrical characteristics section for more
information on the electrical compatibility and details.
Input frequencies supported range from 2 kHz to 155.52
MHz.
Common E1, DS1, OC3 and sub-divisions are supported
as spot frequencies that the DPLLs will directly lock to.
Any input frequency, up to 100 MHz, that is a multiple of
8 kHz can also be locked to via an inbuilt programmable
divider.
An input reference monitor is assigned to each of the 14
inputs. The monitors operate continuously such that at all
times the status of all of the inputs to the device are
known. Each input can be monitored for both frequency
and activity, activity alone, or the monitors can be
disabled.
The frequency monitors have a “hard” (rejection) alarm
limit and a “soft” (flag only) alarm limit for monitoring
frequency, whilst the reference is still within its allowed
frequency band. Each input reference can be
programmed with a priority number allowing references to
be chosen according to the highest priority valid input. The
two paths (T0 and T4) have independent priorities to allow
completely independent operation of the two paths. Both
paths operate either automatic or external source
selection.
For automatic input reference selection, the T0 path has
a more complex state machine than the T4 path.
The T0 and T4 PLL paths support the following common
features:
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Automatic source selection according to input
priorities and quality level
Different quality levels (activity alarm thresholds) for
each input
Variable bandwidth, lock range and damping factor
Direct PLL locking to common SONET/SDH input
frequencies or any multiple of 8 kHz
Automatic mode switching between Free-run, Locked
and Holdover states
Fast detection on input failure and entry into Holdover
mode (holds at the last good frequency value)
Frequency translation between input and output rates
via direct digital synthesis
High accuracy digital architecture for stable PLL
dynamics combined with an APLL for low jitter final
output clocks.
FINAL
Page 9
There are a number of features supported by the T0 path
that are not supported by the T4 path, although these can
also all be externally controlled by software.
The additional T0 features supported are:
Either the software or an internal state machine controls
the operation of the DPLL in the T0 path. The state
machine for the T4 path is very simple and cannot be
manually/externally controlled, however the overall
operation can be controlled by manual reference source
selection. One additional feature of the T4 path is the
ability to measure a phase difference between two inputs.
The T0 path DPLL always produces an output at
77.76 MHz to feed the APLL, regardless of the frequency
selected at the output pins. The T4 path can be operated
at a number of frequencies. This is to enable the
generation of extra output frequencies, which cannot be
easily related to 77.76 MHz. When the T4 path is selected
to lock to the T0 path, the T4 DPLL locks to the 8 kHz from
the T0 DPLL. This is because all of the frequencies of
operation of the T4 path can be divided to 8 kHz and this
will ensure synchronization of all the frequencies within
the two paths.
Both of the DPLLs’ outputs are connected to multiplying
and filtering APLLs. The outputs of these APLLs are
divided making a number of frequencies simultaneously
available for selection at the output clock ports. The
various combinations of DPLL, APLL and divider
configurations allow for generation of a comprehensive
set of frequencies, as listed in Table 14.
To synchronize the lower output frequencies when the T0
PLL is locked to a high frequency reference input, an
additional input is provided. The SYNC2K pin (pin 45) is
used to reset the dividers that generate the 2 kHz and
8 kHz outputs such that the output 2/8 kHz clocks are
lined up with the input 2 kHz. This synchronization
Non-revertive mode
Phase Build-out on source switch (hit-less source
switching)
I/O phase offset control
Greater programmable bandwidth from 0.1 Hz to
70 Hz in 10 steps (T4 path programmable bandwidth
in 3 steps, 18, 35 and 70 Hz)
Noise rejection on low frequency input
Manual Holdover frequency control
Controllable automatic Holdover frequency filtering
Frame Sync pulse alignment.
ACS8520 SETS
DATASHEET
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