ACS8520T Semtech, ACS8520T Datasheet - Page 31

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

There are 2 ways to align the 2 kHz and/or 8 kHz outputs:
1. the use of the External syncing function, or
2. directly locking the Slave to 2 kHz or 8 kHz from the
By directly locking the Slave to the 2 kHz (MFrSync) output
of the Master, all frequencies output from the Slave will
be in phase alignment with the same frequency
generated from the Master. If the Slave is directly locked
to the 8 kHz (FrSync) output from the Master, then all
frequencies except for 2 kHz MFrSync outputs will be in
alignment.
If using the external syncing function then two signals
need to be interconnected between the Master and Slave:
1. the clock and,
2. the Sync signal.
This requires some configuration enhancements. The
Sync signal is not locked to, it is sampled using the
reference clock and used to realign the generated
outputs. The generated outputs are still always locked to
the reference clock and related to each other. Details on
the Master and Slave interconnection wiring and software
configuration can be found in refer to the application note
AN-SETS-2. The following section describes the
resynchronization operation of the MFrSync via the
SYNC2K input.
MFrSync and FrSync Alignment-SYNC2K
The SYNC2K input (pin 45) is monitored by the ACS8520
for consistent phase and correct frequency and if it does
not pass these quality checks, an alarm flag is raised
(Reg. 08, Bit 7 and Reg. 09, Bit 7). The check for
consistent phase involves checking that each input edge
is within an expected timing window. The window size is
set by Reg. 7C, Bits [6:4]. An internal detector senses that
a correct SYNC2K signal is present and only then allows
the signal to resynchronize the internal dividers that
generate the 8 kHz FrSync and 2 kHz MFrSync outputs.
This sequence avoids spurious resynchronizations that
may otherwise occur with connections and
disconnections of the SYNC2K input.
The SYNC2K input will normally be a 2 kHz frequency, only
its falling edge is used. It can however be at a frequencies
of 4 kHz or 8 kHz without any change to the register
setups. Only alignment of the 8 kHz will be achieved in
this case.
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Master.
FINAL
Page 31
Safe sampling of the SYNC2K input is achieved by using
the currently selected clock reference source to do the
input sampling. This is based on the principle that FrSync
alignment is being used on a Slave device that is locked
to the clock reference of a Master device that is also
providing the 2 kHz SYNC2K input. Phase Build-out mode
should be off (Reg. 48, Bit 2 = 0). The 2 kHz MFrSync
output from the Master device has its falling edge aligned
with the falling edge of the other output clocks, hence the
SYNC2K input is normally sampled on the rising edge of
the current input reference clock, in order to provide the
most margin. Some modification of the expected timing of
the SYNC2K with respect to the reference clock can be
achieved via Reg. 7B, Bits [1:0]. This allows for the
SYNC2K input to arrive either half a reference clock cycle
early or up to one and a half cycle late, hence allowing a
safe sampling margin to be maintained.
A different sampling resolution is used depending on the
input reference frequency and the setting of Reg. 7B Bit 6,
cnfg_sync_phase. With this bit Low, the SYNC2K input
sampling has a 6.48 MHz resolution, this being the
preferred reference frequency to lock to from the Master,
in conjunction with the SYNC2K 2 kHz, since it gives the
most timing margin on the sampling and aligns all of the
higher rate OC-3 derived clocks. When Bit 6 is high the
SYNC2K can have a sampling resolution of either
19.44 MHz (when the current locked to reference is
19.44 MHz) or 38.88 MHz (all other frequencies). This
would allow for instance a 19.44 MHz and 2 kHz pair to
be used for Slave synchronization or for Line card
synchronization. Reg. 7B Bit 7, indep_FrSync/MFrSync
controls whether the 2 kHz MFrSync and 8 kHz FrSync
outputs keep their precise alignment with the other
output clocks.
When indep_FrSync/MFrSync Reg. 7B Bit 7 is Low the
FrSyncs and the other higher rate clocks are not
independent and their alignment on the falling 8kHz edge
is maintained. This means that when Bit Sync_OC-N_rates
is High, the OC-N rate dividers and clocks are also
synchronized by the SYNC2K input. On a change of phase
position of the SYNC2K, this could result in a shift in
phase of the 6.48 MHz output clock when a 19.44 MHz
precision is used for the SYNC2K input. To avoid
disturbing any of the output clocks and only align the
MFrSync and FrSync outputs, at the chosen level of
precision, then independent Frame Sync mode can be
used (Reg. 7B, Bit 7 = 1). Edge alignment of the FrSync
output with other clocks outputs may then change
depending on the SYNC2K sampling precision used. For
ACS8520 SETS
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