ACS8520T Semtech, ACS8520T Datasheet - Page 21

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Phase Detectors
A Phase and Frequency detector is used to compare input
and feedback clocks. This operates at input frequencies
up to 77.76 MHz. The whole DPLL can operate at spot
frequencies from 2 kHz up to 77.76 MHz (155.52 MHz is
internally divided down to 77.76 MHz). A common
arrangement however is to use Lock8k mode (See
Reg. 22 to 2D, Bit 6) where all input frequencies are
divided down to 8 kHz internally. Marginally better MTIE
figures may be possible in direct lock mode due to more
regular phase updates. This direct locking capability is
one of the unique features of the ACS8520.
A patented multi-phase detector is used in order to give
an infinitesimally small input phase resolution combined
with large jitter tolerance. The following phase detectors
are used:
The phase detectors can be configured to be immune to
occasional missing input clock pulses by using nearest
edge detection (±180° capture) or the normal ±360°
phase capture range which gives frequency locking. The
device will automatically switch to nearest edge locking
when the multi-UI phase detector is not enabled, and the
other phase detectors have detected that phase lock has
been achieved. It is possible to disable the selection of
nearest edge locking via Reg. 03 Bit 6 set to 1. In this
setting, frequency locking will always be enabled.
The balance between the first two types of phase detector
employed can be adjusted via registers 6A to 6D. The
default settings should be sufficient for all modes.
Adjustment of these settings affects only small signal
overshoot and bandwidth.
The multi-cycle phase detector is enabled via Reg. 74,
Bit 6 set to 1 and the range is set in exponentially
increasing steps from ±1 UI, 3 UI, 7 UI, 15 UI … up to
8191 UI via Reg. 74, Bits [3:0]. When this detector is
enabled it keeps a track of the correct phase position over
many cycles of phase difference to give excellent jitter
tolerance. This provides an alternative to switching to
Lock8k mode as a method of achieving high jitter
tolerance.
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Phase and frequency detector (±360° or ±180°
range)
An Early/ Late Phase detector for fine resolution
A multi-cycle phase detector for large input jitter
tolerance (up to 8191 UI), which captures and
remembers phase differences of many cycles
between input and feedback clocks.
FINAL
Page 21
An additional control (Reg. 74 Bit 5) enables the multi-
phase detector value to be used in the final phase value
as part of the DPLL loop. When enabled by setting High,
the multi cycle phase value will be used in the loop and
gives faster pull in (but more overshoot). The
characteristics of the loop will be similar to Lock8k mode
where again large input phase differences contribute to
the loop dynamics. Setting the bit Low only uses a max
figure of 360 degrees in the loop and will give slower pull-
in but gives less overshoot. The final phase position that
the loop has to pull in to is still tracked and remembered
by the multi-cycle phase detector in either case.
Phase Lock/Loss Detection
Phase lock/loss detection is handled in several ways.
Phase loss can be triggered from:
Each of these sources of phase loss indication is
individually enabled via register bits (see Reg. 73, 74 and
4D). Phase lock or lost is used to determine whether to
switch to nearest edge locking and whether to use
acquisition or normal bandwidth settings for the DPLL.
Acquisition bandwidth is used for faster pull in from an
unlocked state.
The coarse phase lock detector detects phase differences
of n cycles between input and feedback clocks, where n is
set by Reg. 74, Bits [3:0]; the same register that is used
for the coarse phase detector range, since these
functions go hand in hand. This detector may be used in
the case where it is required that a phase loss indication
is not given for reasonable amounts of input jitter and so
the fine phase loss detector is disabled and the coarse
detector is used instead.
Damping Factor Programmability
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. Many of
the specifications (e.g. GR-1244-CORE
G.813
0.2 dB. GR-253
less than 0.1 dB. To accommodate the required levels of
transfer gain, the ACS8520 provides a choice of damping
The fine phase lock detector, which measures the
phase between input and feedback clock
The coarse phase lock detector, which monitors whole
cycle slips
Detection that the DPLL is at min or max frequency
Detection of no activity on the input.
[11]
) specify a wander transfer gain of less than
[17]
specifies jitter (not wander) transfer of
ACS8520 SETS
[19]
DATASHEET
www.semtech.com
, G.812
[10]
and