ACS8520T Semtech, ACS8520T Datasheet - Page 56

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Table 30 Register Map (cont...)
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
RO = Read Only
R/W = Read/Write
cnfg_output_frequency (R/W)
cnfg_T4_DPLL_frequency (R/W)
cnfg_T0_DPLL_frequency (R/W)
cnfg_T4_DPLL_bw (R/W)
cnfg_T0_DPLL_locked_bw (R/W)
cnfg_T0_DPLL_acq_bw (R/W)
cnfg_T4_DPLL_damping (R/W)
cnfg_T0_DPLL_damping (R/W)
cnfg_T4_DPLL_PD2_gain (R/W)
cnfg_T0_DPLL_PD2_gain (R/W)
cnfg_phase_offset (R/W)
cnfg_PBO_phase_offset (R/W)
cnfg_phase_loss_fine_limit (R/W) 73 A2
cnfg_phase_loss_coarse_limit
(R/W)
cnfg_phasemon (R/W)
sts_current_phase (RO)
cnfg_phase_alarm_timeout
(R/W)
cnfg_sync_pulses (R/W)
cnfg_sync_phase (R/W)
cnfg_sync_monitor (R/W)
cnfg_interrupt (R/W)
cnfg_protection(R/W)
cnfg_uPsel (R/W)
Register Name
(TO7 to TO11) 63 F6
(TO1 & TO2) 60 85
(TO3 & TO4) 61 86
(TO5 & TO6) 62 8A
[15:8] 71 00
[15:8] 78 00
[7:0] 70 00
[7:0] 77 00
6C C2 T4_PD2_gain_
6D C2 T0_PD2_gain_
72 00
7B 00 indep_FrSync/
7D 02
64 01
65 01 T4 for
66 00
67 0B
69 0F
6A
6B 13
74 85 Coarse limit
76 06 Input noise
79 32
7A
7C 2B ph_offset_
7E
7F
13
00 2 k/8 k out
02
*
85
MFrSync
enable
measuring T0
phase
enable
enable
Fine limit
Phase loss
enable (1)
Phase loss
enable (2)
window enable
from T4
MFrSync
ramp
7 (MSB)
FrSync enable
Auto Disable
T4 output
T4 APLL for T0
E1/DS1
No activity for
phase loss
Wide range
enable
Sync_OC-N_
rates
output_freq_2 (TO2)
output_freq_4 (TO4)
output_freq_6 (TO6)
6
T4_PD2_gain_alog_8K [6:4]
T0_PD2_gain_alog_8K [6:4]
T4_PD2_gain_alog [6:4]
T0_PD2_gain_alog [6:4]
Sync_monitor_limit
TO9 enable
AMI Duty cycle T4 SONET/
Test bit
Set to 1
Enable Multi
Phase resp.
FINAL
Page 56
T0 Freq to T4 APLL
5
TO8 enable
SDH selection
phase_offset_value[15:8]
phase_offset_value[7:0]
current_phase[15:8]
current_phase[7:0]
4
protection_value
Data Bit
Timeout value in 2s intervals [5:0]
8 k invert
PBO_phase_offset [5:0]
3
T0_DPLL_acquisition_bandwidth [4:0]
Phase loss coarse limit in UI p-p [3:0]
T0_DPLL_locked_bandwidth [4:0]
8 k pulse
enable
GPO interrupt
enable
Microprocessor type (*Default value depends on
Sync_reference_source
output_freq_7 <TO7>
output_freq_1 (TO1)
output_freq_3 (TO3)
output_freq_5 (TO5)
ACS8520 SETS
2
phase_loss_fine_limit [2:0]
T4_PD2_gain_digital [2:0]
T0_PD2_gain_digital [2:0]
value on UPSEL[2:0] pins)
T4_DPLL_frequency
T0_DPLL_frequency
T4_damping [2:0]
T0_damping [2:0]
2 k invert
Interrupt
tristate
enable
T4_DPLL_bandwidth [1:0]
1
DATASHEET
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Sync_phase
2 k pulse
enable
Interrupt
polarity
enable
0 (LSB)