ACS8520T Semtech, ACS8520T Datasheet - Page 88

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Address (hex):
Address (hex):
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Register Name
auto_BW_sel
Register Name
Bit No.
Bit No.
Bit 7
[6:4]
[2:0]
Bit 7
[7:0]
7
3
3B
3C
cnfg_auto_bw_sel
Description
auto_BW_sel
Bit to select locked bandwidth (Reg. 67) or
acquisition bandwidth (Reg. 69) for the T0 DPLL
Not used.
T0_lim_int
When set to 1 the integral path value of the DPLL is
limited or frozen when the DPLL reaches either min
or max frequency. This can be used to minimize
subsequent overshoot when the DPLL is pulling in.
Note that when this happens, the reported
frequency value via current_DPLL_freq (Reg. 0C, 0D
and 07) is also frozen.
Not used.
cnfg_nominal_frequency
[7:0]
Description
cnfg_nominal_frequency_value[7:0]
Bit 6
Bit 6
Bit 5
Bit 5
cnfg_nominal_frequency_value[7:0]
Description
Description
Bit 4
Bit 4
FINAL
Page 88
(R/W) Register to select
automatic BW selection for the T0
DPLL path
T0_lim_int
(R/W) Bits [7:0] of the register
used to calibrate the crystal
oscillator used to clock the
device.
Bit Value
Bit Value
Bit 3
Bit 3
1
0
1
0
-
-
-
Value Description
Automatically selects either locked or acquisition
bandwidth as appropriate
Always selects locked bandwidth
-
DPLL value frozen
DPLL not frozen
-
Value Description
See register description of Reg. 3D
(cnfg_nominal_frequency_value[15:8]).
Bit 2
Bit 2
Default Value
Default Value
ACS8520 SETS
Bit 1
Bit 1
DATASHEET
www.semtech.com
1111 1011
1001 1001
Bit 0
Bit 0