ACS8520T Semtech, ACS8520T Datasheet - Page 25

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Jitter and Wander Transfer
The ACS8520 has a programmable jitter and wander
transfer characteristic. This is set by the DPLL bandwidth.
The -3 dB jitter transfer attenuation point can be set in the
range from 0.1 Hz to 70 Hz in 10 steps. The wander and
jitter transfer characteristic is shown in Figure 8. Wander
on the local oscillator clock will not have a significant
effect on the output clock whilst in Locked mode, provided
that the DPLL bandwidth is set high enough so that the
DPLL can compensate quickly enough for any frequency
changes in the crystal.
In Free-run or Holdover mode wander on the crystal is
more significant. Variation in crystal temperature or
supply voltage both cause drifts in operating frequency,
as does ageing. These effects must be limited by careful
selection of a suitable component for the local oscillator,
as specified in the section See Local Oscillator Clock.
Phase Build-out
Phase Build-out (PBO) is the function to minimize phase
transients on the output SEC clock during input reference
switching. If the currently selected input reference clock
source is lost (due to a short interruption, out of frequency
detection, or complete loss of reference) the second, next
highest priority reference source will be selected, and a
PBO event triggered.
Figure 8 Sample of Wander and Jitter Measured Transfer Characteristics
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
FINAL
Page 25
ITU-T G.813
term phase transient response, resulting from a switch
from one clock source to another, with Holdover mode
entered in between, should be a maximum of 1 µs over a
15 second interval. The maximum phase transient or
jump should be less than 120 ns at a rate of change of
less than 7.5 ppm and the Holdover performance should
be better than 0.05 ppm. The ACS8520 performance is
well within this requirement. The typical phase
disturbance on clock reference source switching will be
less than 5 ns on the ACS8520.
When a PBO event is triggered, the device enters a
temporary Holdover state. When in this temporary state,
the phase of the input reference is measured, relative to
the output. The device then automatically accounts for
any measured phase difference and adds the appropriate
phase offset into the DPLL to compensate. Following a
PBO event, whatever the phase difference on change of
input, the output phase transient is minimized to be no
greater than 5 ns.
On the ACS8520, PBO can be enabled, disabled or frozen
using the microprocessor interface. By default, it is
enabled. When PBO is enabled, PBO can also be frozen (at
the current offset setting). The device will then ignore any
further PBO events occurring on any subsequent
[11]
states that the maximum allowable short-
ACS8520 SETS
DATASHEET
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