ACS8520T Semtech, ACS8520T Datasheet - Page 28

• Manufacturer Part Number: ACS8520T
• Description: Synchronous Equipment Timing Source (SETS) for Stratum 3/4E/4 and SMC Systems
• Manufacturer: Semtech

Figure 10 Minimum Input Jitter Tolerance (DS1/E1)
Using the DPLLs for Accurate Frequency and Phase
Reporting
The frequency monitors in the ACS8520 perform
frequency monitoring with a programmable acceptable
limit of up to ±60.96 ppm. The resolution of the
measurement is 3.8 ppm and the measured frequency
can be read back from Reg. 4C, with channel selection at
Reg. 4B. For more accurate measurement of both
frequency and phase, the T0 and T4 DPLLs and their
phase detectors, can be used to monitor both input
frequency and phase. The T0 DPLL is always monitoring
the currently locked to source, but if the T4 path is not
used then the T4 DPLL can be used as a roving phase and
frequency meter. Via software control it could be switched
to monitor each input in turn and both the phase and
frequency can be reported with a very fine resolution.
The registers sts_current_dpll_frequency (Reg. 0C,
Reg. 0D and Reg. 07) report the frequency of either the
T0 or T4 DPLL with respect to the external crystal XO
frequency (after calibration via Reg. 3C, 3D if used). The
selection of T4 or T0 DPLL reporting is made via Reg. 4B,
Bit 4. The value is a 19-bit signed number with one LSB
representing 0.0003068 ppm (range of ±80 ppm). This
value is actually the integral path value in the DPLL, and
as such corresponds to an averaged measurement of the
Revision 3.02/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Table 10 Amplitude and Frequency Values for Jitter Tolerance (DS1/E1)
Peak-to-peak Jitter and Wander Amplitude
(log scale)
DS1
E1
Type
A1
A2
GR-1244-CORE
ITU G.823
f1
Spec.
[13]
[19]
5
1.5
f2
Amplitude (UI p-p)
A1
0.1
0.2
f3
A2
FINAL
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input frequency, with an averaging time inversely
proportional to the DPLL bandwidth setting. Reading this
regularly can show how the currently locked source is
varying in value e.g. due to frequency wander on its input.
The input phase, as seen at the DPLL phase detector, can
be read back from register sts_current_phase, Reg. 77
and 78. T0 or T4 DPLL phase detector reporting is again
controlled by Reg. 4B, Bit 4. One LSB corresponds to
approximately 0.7 degrees phase difference. For the T0
DPLL this will be reporting the phase difference between
the input and the internal feedback clock. The phase
result is internally averaged or filtered with a -3 dB
attenuation point at approximately 100 Hz. For low DPLL
bandwidths, 0.1 Hz for example, this measured phase
information from the T0 DPLL gives input phase wander in
the frequency band from for example 0.1 Hz to 100 Hz.
This could be used to give a crude input MTIE
measurement up to an observation period of
approximately 1000 seconds using external software.
In addition, the T4 DPLL phase detector can be used to
make a phase measurement between two inputs.
Reg. 65, Bit 7 is used to switch one input to the T4 phase
detector over to the current T0 input. The other phase
detector input remains connected to the selected T4 input
source, the selected source can be forced via Reg. 35,
F1
f4
Jitter and Wander Frequency (log scale)
500
2.4 k
F2
Frequency (Hz)
8 k
18 k
F8530D_004MINIPJITTOLDS1E1_02
F3
ACS8520 SETS
40 k
100
F4
DATASHEET
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